1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Transparent non-programmable DRM bridges 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun This binding supports transparent non-programmable bridges that don't require 15*4882a593Smuzhiyun any configuration, with a single input and a single output. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun oneOf: 20*4882a593Smuzhiyun - items: 21*4882a593Smuzhiyun - enum: 22*4882a593Smuzhiyun - ti,ths8134a 23*4882a593Smuzhiyun - ti,ths8134b 24*4882a593Smuzhiyun - const: ti,ths8134 25*4882a593Smuzhiyun - enum: 26*4882a593Smuzhiyun - adi,adv7123 27*4882a593Smuzhiyun - dumb-vga-dac 28*4882a593Smuzhiyun - ti,opa362 29*4882a593Smuzhiyun - ti,ths8134 30*4882a593Smuzhiyun - ti,ths8135 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ports: 33*4882a593Smuzhiyun type: object 34*4882a593Smuzhiyun description: | 35*4882a593Smuzhiyun This device has two video ports. Their connections are modeled using the 36*4882a593Smuzhiyun OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. 37*4882a593Smuzhiyun properties: 38*4882a593Smuzhiyun '#address-cells': 39*4882a593Smuzhiyun const: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun '#size-cells': 42*4882a593Smuzhiyun const: 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun port@0: 45*4882a593Smuzhiyun type: object 46*4882a593Smuzhiyun description: The bridge input 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun port@1: 49*4882a593Smuzhiyun type: object 50*4882a593Smuzhiyun description: The bridge output 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun required: 53*4882a593Smuzhiyun - port@0 54*4882a593Smuzhiyun - port@1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun additionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enable-gpios: 59*4882a593Smuzhiyun maxItems: 1 60*4882a593Smuzhiyun description: GPIO controlling bridge enable 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vdd-supply: 63*4882a593Smuzhiyun maxItems: 1 64*4882a593Smuzhiyun description: Power supply for the bridge 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunrequired: 67*4882a593Smuzhiyun - compatible 68*4882a593Smuzhiyun - ports 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunadditionalProperties: false 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunexamples: 73*4882a593Smuzhiyun - | 74*4882a593Smuzhiyun bridge { 75*4882a593Smuzhiyun compatible = "ti,ths8134a", "ti,ths8134"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun ports { 78*4882a593Smuzhiyun #address-cells = <1>; 79*4882a593Smuzhiyun #size-cells = <0>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun port@0 { 82*4882a593Smuzhiyun reg = <0>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun vga_bridge_in: endpoint { 85*4882a593Smuzhiyun remote-endpoint = <&tcon0_out_vga>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun port@1 { 90*4882a593Smuzhiyun reg = <1>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun vga_bridge_out: endpoint { 93*4882a593Smuzhiyun remote-endpoint = <&vga_con_in>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun... 100