1*4882a593Smuzhiyunsii902x HDMI bridge bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: "sil,sii9022" 5*4882a593Smuzhiyun - reg: i2c address of the bridge 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunOptional properties: 8*4882a593Smuzhiyun - interrupts: describe the interrupt line used to inform the host 9*4882a593Smuzhiyun about hotplug events. 10*4882a593Smuzhiyun - reset-gpios: OF device-tree gpio specification for RST_N pin. 11*4882a593Smuzhiyun - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V) 12*4882a593Smuzhiyun - cvcc12-supply: Digital Core Supply Voltage (1.2V) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun HDMI audio properties: 15*4882a593Smuzhiyun - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin 16*4882a593Smuzhiyun is wired, <1> if the both are wired. HDMI audio is 17*4882a593Smuzhiyun configured only if this property is found. 18*4882a593Smuzhiyun - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3 19*4882a593Smuzhiyun Each integer indicates which i2s pin is connected to which 20*4882a593Smuzhiyun audio fifo. The first integer selects i2s audio pin for the 21*4882a593Smuzhiyun first audio fifo#0 (HDMI channels 1&2), second for fifo#1 22*4882a593Smuzhiyun (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s 23*4882a593Smuzhiyun pins (SD0 - SD3). Any i2s pin can be connected to any fifo, 24*4882a593Smuzhiyun but there can be no gaps. E.g. an i2s pin must be mapped to 25*4882a593Smuzhiyun fifo#0 and fifo#1 before mapping a channel to fifo#2. Default 26*4882a593Smuzhiyun value is <0>, describing SD0 pin beiging routed to hdmi audio 27*4882a593Smuzhiyun fifo #0. 28*4882a593Smuzhiyun - clocks: phandle and clock specifier for each clock listed in 29*4882a593Smuzhiyun the clock-names property 30*4882a593Smuzhiyun - clock-names: "mclk" 31*4882a593Smuzhiyun Describes SII902x MCLK input. MCLK can be used to produce 32*4882a593Smuzhiyun HDMI audio CTS values. This property follows 33*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt 34*4882a593Smuzhiyun consumer binding. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun If HDMI audio is configured the sii902x device becomes an I2S 37*4882a593Smuzhiyun and/or spdif audio codec component (e.g a digital audio sink), 38*4882a593Smuzhiyun that can be used in configuring a full audio devices with 39*4882a593Smuzhiyun simple-card or audio-graph-card binding. See their binding 40*4882a593Smuzhiyun documents on how to describe the way the sii902x device is 41*4882a593Smuzhiyun connected to the rest of the audio system: 42*4882a593Smuzhiyun Documentation/devicetree/bindings/sound/simple-card.yaml 43*4882a593Smuzhiyun Documentation/devicetree/bindings/sound/audio-graph-card.txt 44*4882a593Smuzhiyun Note: In case of the audio-graph-card binding the used port 45*4882a593Smuzhiyun index should be 3. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunOptional subnodes: 48*4882a593Smuzhiyun - video input: this subnode can contain a video input port node 49*4882a593Smuzhiyun to connect the bridge to a display controller output (See this 50*4882a593Smuzhiyun documentation [1]). 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun[1]: Documentation/devicetree/bindings/media/video-interfaces.txt 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExample: 55*4882a593Smuzhiyun hdmi-bridge@39 { 56*4882a593Smuzhiyun compatible = "sil,sii9022"; 57*4882a593Smuzhiyun reg = <0x39>; 58*4882a593Smuzhiyun reset-gpios = <&pioA 1 0>; 59*4882a593Smuzhiyun iovcc-supply = <&v3v3_hdmi>; 60*4882a593Smuzhiyun cvcc12-supply = <&v1v2_hdmi>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #sound-dai-cells = <0>; 63*4882a593Smuzhiyun sil,i2s-data-lanes = < 0 1 2 >; 64*4882a593Smuzhiyun clocks = <&mclk>; 65*4882a593Smuzhiyun clock-names = "mclk"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun ports { 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <0>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun port@0 { 72*4882a593Smuzhiyun reg = <0>; 73*4882a593Smuzhiyun bridge_in: endpoint { 74*4882a593Smuzhiyun remote-endpoint = <&dc_out>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79