1*4882a593SmuzhiyunROHM BU18TL82/BU18RL82 Clockless Link-BD Serializer/Deserializer bridge bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: "rohm,bu18tl82" or "rohm,bu18rl82" 5*4882a593Smuzhiyun - reg: i2c address of the bridge 6*4882a593Smuzhiyun - serdes-init-sequence: register initial code from Rohm vendor 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunoptional properties: 9*4882a593Smuzhiyun - reset-gpios: a GPIO spec for the reset pin 10*4882a593Smuzhiyun - enable-gpios: a GPIO spec for the enable pin 11*4882a593Smuzhiyun - power-supply: Reference to the regulator powering the serdes power supply pins 12*4882a593Smuzhiyun - sel-mipi: string property for mipi dsi data stream input 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun panel { 18*4882a593Smuzhiyun compatible = "simple-panel"; 19*4882a593Smuzhiyun backlight = <&backlight>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun display-timings { 22*4882a593Smuzhiyun native-mode = <&timing0>; 23*4882a593Smuzhiyun timing0: timing0 { 24*4882a593Smuzhiyun clock-frequency = <87000000>; 25*4882a593Smuzhiyun hactive = <1920>; 26*4882a593Smuzhiyun vactive = <720>; 27*4882a593Smuzhiyun hfront-porch = <32>; 28*4882a593Smuzhiyun hsync-len = <10>; 29*4882a593Smuzhiyun hback-porch = <22>; 30*4882a593Smuzhiyun vfront-porch = <10>; 31*4882a593Smuzhiyun vsync-len = <4>; 32*4882a593Smuzhiyun vback-porch = <7>; 33*4882a593Smuzhiyun hsync-active = <0>; 34*4882a593Smuzhiyun vsync-active = <0>; 35*4882a593Smuzhiyun de-active = <0>; 36*4882a593Smuzhiyun pixelclk-active = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ports { 41*4882a593Smuzhiyun #address-cells = <1>; 42*4882a593Smuzhiyun #size-cells = <0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun port@0 { 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun panel0_in_i2c2_bu18rl82: endpoint { 47*4882a593Smuzhiyun remote-endpoint = <&i2c2_bu18rl82_out_panel0>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&dsi { 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ports { 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <0>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun port@1 { 62*4882a593Smuzhiyun reg = <1>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun dsi0_out_i2c2_bu18tl82: endpoint { 65*4882a593Smuzhiyun remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&i2c2 { 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun bu18tl82: bu18tl82@10 { 75*4882a593Smuzhiyun compatible = "rohm,bu18tl82"; 76*4882a593Smuzhiyun reg = <0x10>; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun pinctrl-0 = <&ser0_rst_gpio>; 79*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 80*4882a593Smuzhiyun sel-mipi; 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun serdes-init-sequence = [ 84*4882a593Smuzhiyun /* TL82 Pattern Gen Set 1 85*4882a593Smuzhiyun * Horizontal Gray Scale 256 steps 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun 040A 0010 88*4882a593Smuzhiyun 040B 0080 89*4882a593Smuzhiyun 040C 0080 90*4882a593Smuzhiyun 040D 0080 91*4882a593Smuzhiyun 0444 0019 92*4882a593Smuzhiyun 0445 0020 93*4882a593Smuzhiyun 0446 001f 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun ... 96*4882a593Smuzhiyun ]; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun ports { 99*4882a593Smuzhiyun #address-cells = <1>; 100*4882a593Smuzhiyun #size-cells = <0>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun port@0 { 103*4882a593Smuzhiyun reg = <0>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun i2c2_bu18tl82_in_dsi0: endpoint { 106*4882a593Smuzhiyun remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun port@1 { 111*4882a593Smuzhiyun reg = <1>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { 114*4882a593Smuzhiyun remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun bu18rl82: bu18rl82@30 { 121*4882a593Smuzhiyun compatible = "rohm,bu18rl82"; 122*4882a593Smuzhiyun reg = <0x30>; 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun serdes-init-sequence = [ 125*4882a593Smuzhiyun /* RL82 Pattern Gen Set 126*4882a593Smuzhiyun * Vertical Gray Scale Color Bar 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun 060A 00B0 129*4882a593Smuzhiyun 060B 00FF 130*4882a593Smuzhiyun 060C 00FF 131*4882a593Smuzhiyun 060D 00FF 132*4882a593Smuzhiyun 0644 0019 133*4882a593Smuzhiyun 0645 0020 134*4882a593Smuzhiyun 0646 001f 135*4882a593Smuzhiyun ... 136*4882a593Smuzhiyun ]; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun ports { 139*4882a593Smuzhiyun #address-cells = <1>; 140*4882a593Smuzhiyun #size-cells = <0>; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun port@0 { 143*4882a593Smuzhiyun reg = <0>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { 146*4882a593Smuzhiyun remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun port@1 { 151*4882a593Smuzhiyun reg = <1>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun i2c2_bu18rl82_out_panel0: endpoint { 154*4882a593Smuzhiyun remote-endpoint = <&panel0_in_i2c2_bu18rl82>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun}; 160