xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Renesas R-Car LVDS Encoder
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14*4882a593Smuzhiyun  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    enum:
19*4882a593Smuzhiyun      - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20*4882a593Smuzhiyun      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21*4882a593Smuzhiyun      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22*4882a593Smuzhiyun      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23*4882a593Smuzhiyun      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24*4882a593Smuzhiyun      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25*4882a593Smuzhiyun      - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26*4882a593Smuzhiyun      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
27*4882a593Smuzhiyun      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
28*4882a593Smuzhiyun      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
29*4882a593Smuzhiyun      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
30*4882a593Smuzhiyun      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
31*4882a593Smuzhiyun      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
32*4882a593Smuzhiyun      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
33*4882a593Smuzhiyun      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
34*4882a593Smuzhiyun      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
35*4882a593Smuzhiyun      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  reg:
38*4882a593Smuzhiyun    maxItems: 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  clocks:
41*4882a593Smuzhiyun    minItems: 1
42*4882a593Smuzhiyun    maxItems: 4
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  clock-names:
45*4882a593Smuzhiyun    minItems: 1
46*4882a593Smuzhiyun    maxItems: 4
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun  resets:
49*4882a593Smuzhiyun    maxItems: 1
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  ports:
52*4882a593Smuzhiyun    type: object
53*4882a593Smuzhiyun    description: |
54*4882a593Smuzhiyun      This device has two video ports. Their connections are modelled using the
55*4882a593Smuzhiyun      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
56*4882a593Smuzhiyun      Each port shall have a single endpoint.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun    properties:
59*4882a593Smuzhiyun      '#address-cells':
60*4882a593Smuzhiyun        const: 1
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun      '#size-cells':
63*4882a593Smuzhiyun        const: 0
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun      port@0:
66*4882a593Smuzhiyun        type: object
67*4882a593Smuzhiyun        description: Parallel RGB input port
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun      port@1:
70*4882a593Smuzhiyun        type: object
71*4882a593Smuzhiyun        description: LVDS output port
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun    required:
74*4882a593Smuzhiyun      - port@0
75*4882a593Smuzhiyun      - port@1
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun    additionalProperties: false
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun  power-domains:
80*4882a593Smuzhiyun    maxItems: 1
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun  renesas,companion:
83*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
84*4882a593Smuzhiyun    description:
85*4882a593Smuzhiyun      phandle to the companion LVDS encoder. This property is mandatory
86*4882a593Smuzhiyun      for the first LVDS encoder on D3 and E3 SoCs, and shall point to
87*4882a593Smuzhiyun      the second encoder to be used as a companion in dual-link mode. It
88*4882a593Smuzhiyun      shall not be set for any other LVDS encoder.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyunrequired:
91*4882a593Smuzhiyun  - compatible
92*4882a593Smuzhiyun  - reg
93*4882a593Smuzhiyun  - clocks
94*4882a593Smuzhiyun  - power-domains
95*4882a593Smuzhiyun  - resets
96*4882a593Smuzhiyun  - ports
97*4882a593Smuzhiyun
98*4882a593Smuzhiyunif:
99*4882a593Smuzhiyun  properties:
100*4882a593Smuzhiyun    compatible:
101*4882a593Smuzhiyun      enum:
102*4882a593Smuzhiyun        - renesas,r8a774c0-lvds
103*4882a593Smuzhiyun        - renesas,r8a77990-lvds
104*4882a593Smuzhiyun        - renesas,r8a77995-lvds
105*4882a593Smuzhiyunthen:
106*4882a593Smuzhiyun  properties:
107*4882a593Smuzhiyun    clocks:
108*4882a593Smuzhiyun      minItems: 1
109*4882a593Smuzhiyun      maxItems: 4
110*4882a593Smuzhiyun      items:
111*4882a593Smuzhiyun        - description: Functional clock
112*4882a593Smuzhiyun        - description: EXTAL input clock
113*4882a593Smuzhiyun        - description: DU_DOTCLKIN0 input clock
114*4882a593Smuzhiyun        - description: DU_DOTCLKIN1 input clock
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun    clock-names:
117*4882a593Smuzhiyun      minItems: 1
118*4882a593Smuzhiyun      maxItems: 4
119*4882a593Smuzhiyun      items:
120*4882a593Smuzhiyun        - const: fck
121*4882a593Smuzhiyun        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
122*4882a593Smuzhiyun        # These clocks are optional.
123*4882a593Smuzhiyun        - enum:
124*4882a593Smuzhiyun            - extal
125*4882a593Smuzhiyun            - dclkin.0
126*4882a593Smuzhiyun            - dclkin.1
127*4882a593Smuzhiyun        - enum:
128*4882a593Smuzhiyun            - extal
129*4882a593Smuzhiyun            - dclkin.0
130*4882a593Smuzhiyun            - dclkin.1
131*4882a593Smuzhiyun        - enum:
132*4882a593Smuzhiyun            - extal
133*4882a593Smuzhiyun            - dclkin.0
134*4882a593Smuzhiyun            - dclkin.1
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun  required:
137*4882a593Smuzhiyun    - clock-names
138*4882a593Smuzhiyun
139*4882a593Smuzhiyunelse:
140*4882a593Smuzhiyun  properties:
141*4882a593Smuzhiyun    clocks:
142*4882a593Smuzhiyun      maxItems: 1
143*4882a593Smuzhiyun      items:
144*4882a593Smuzhiyun        - description: Functional clock
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun    clock-names:
147*4882a593Smuzhiyun      maxItems: 1
148*4882a593Smuzhiyun      items:
149*4882a593Smuzhiyun        - const: fck
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun    renesas,companion: false
152*4882a593Smuzhiyun
153*4882a593SmuzhiyunadditionalProperties: false
154*4882a593Smuzhiyun
155*4882a593Smuzhiyunexamples:
156*4882a593Smuzhiyun  - |
157*4882a593Smuzhiyun    #include <dt-bindings/clock/renesas-cpg-mssr.h>
158*4882a593Smuzhiyun    #include <dt-bindings/power/r8a7795-sysc.h>
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun    lvds@feb90000 {
161*4882a593Smuzhiyun        compatible = "renesas,r8a7795-lvds";
162*4882a593Smuzhiyun        reg = <0xfeb90000 0x14>;
163*4882a593Smuzhiyun        clocks = <&cpg CPG_MOD 727>;
164*4882a593Smuzhiyun        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
165*4882a593Smuzhiyun        resets = <&cpg 727>;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun        ports {
168*4882a593Smuzhiyun            #address-cells = <1>;
169*4882a593Smuzhiyun            #size-cells = <0>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun            port@0 {
172*4882a593Smuzhiyun                reg = <0>;
173*4882a593Smuzhiyun                lvds_in: endpoint {
174*4882a593Smuzhiyun                    remote-endpoint = <&du_out_lvds0>;
175*4882a593Smuzhiyun                };
176*4882a593Smuzhiyun            };
177*4882a593Smuzhiyun            port@1 {
178*4882a593Smuzhiyun                reg = <1>;
179*4882a593Smuzhiyun                lvds_out: endpoint {
180*4882a593Smuzhiyun                    remote-endpoint = <&panel_in>;
181*4882a593Smuzhiyun                };
182*4882a593Smuzhiyun            };
183*4882a593Smuzhiyun        };
184*4882a593Smuzhiyun    };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun  - |
187*4882a593Smuzhiyun    #include <dt-bindings/clock/renesas-cpg-mssr.h>
188*4882a593Smuzhiyun    #include <dt-bindings/power/r8a77990-sysc.h>
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun    lvds0: lvds@feb90000 {
191*4882a593Smuzhiyun        compatible = "renesas,r8a77990-lvds";
192*4882a593Smuzhiyun        reg = <0xfeb90000 0x20>;
193*4882a593Smuzhiyun        clocks = <&cpg CPG_MOD 727>,
194*4882a593Smuzhiyun                 <&x13_clk>,
195*4882a593Smuzhiyun                 <&extal_clk>;
196*4882a593Smuzhiyun        clock-names = "fck", "dclkin.0", "extal";
197*4882a593Smuzhiyun        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
198*4882a593Smuzhiyun        resets = <&cpg 727>;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun        renesas,companion = <&lvds1>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun        ports {
203*4882a593Smuzhiyun            #address-cells = <1>;
204*4882a593Smuzhiyun            #size-cells = <0>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun            port@0 {
207*4882a593Smuzhiyun                reg = <0>;
208*4882a593Smuzhiyun                lvds0_in: endpoint {
209*4882a593Smuzhiyun                    remote-endpoint = <&du_out_lvds0>;
210*4882a593Smuzhiyun                };
211*4882a593Smuzhiyun            };
212*4882a593Smuzhiyun            port@1 {
213*4882a593Smuzhiyun                reg = <1>;
214*4882a593Smuzhiyun                lvds0_out: endpoint {
215*4882a593Smuzhiyun                    remote-endpoint = <&panel_in1>;
216*4882a593Smuzhiyun                };
217*4882a593Smuzhiyun            };
218*4882a593Smuzhiyun        };
219*4882a593Smuzhiyun    };
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun    lvds1: lvds@feb90100 {
222*4882a593Smuzhiyun        compatible = "renesas,r8a77990-lvds";
223*4882a593Smuzhiyun        reg = <0xfeb90100 0x20>;
224*4882a593Smuzhiyun        clocks = <&cpg CPG_MOD 727>,
225*4882a593Smuzhiyun                 <&x13_clk>,
226*4882a593Smuzhiyun                 <&extal_clk>;
227*4882a593Smuzhiyun        clock-names = "fck", "dclkin.0", "extal";
228*4882a593Smuzhiyun        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229*4882a593Smuzhiyun        resets = <&cpg 726>;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun        ports {
232*4882a593Smuzhiyun            #address-cells = <1>;
233*4882a593Smuzhiyun            #size-cells = <0>;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun            port@0 {
236*4882a593Smuzhiyun                reg = <0>;
237*4882a593Smuzhiyun                lvds1_in: endpoint {
238*4882a593Smuzhiyun                    remote-endpoint = <&du_out_lvds1>;
239*4882a593Smuzhiyun                };
240*4882a593Smuzhiyun            };
241*4882a593Smuzhiyun            port@1 {
242*4882a593Smuzhiyun                reg = <1>;
243*4882a593Smuzhiyun                lvds1_out: endpoint {
244*4882a593Smuzhiyun                    remote-endpoint = <&panel_in2>;
245*4882a593Smuzhiyun                };
246*4882a593Smuzhiyun            };
247*4882a593Smuzhiyun        };
248*4882a593Smuzhiyun    };
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun...
251