1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk> 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Chrontel CH7033 Video Encoder Device Tree Bindings 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Lubomir Rintel <lkundrak@v3.sk> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun const: chrontel,ch7033 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun description: I2C address of the device 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ports: 22*4882a593Smuzhiyun type: object 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun properties: 25*4882a593Smuzhiyun port@0: 26*4882a593Smuzhiyun type: object 27*4882a593Smuzhiyun description: | 28*4882a593Smuzhiyun Video port for RGB input. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun port@1: 31*4882a593Smuzhiyun type: object 32*4882a593Smuzhiyun description: | 33*4882a593Smuzhiyun DVI port, should be connected to a node compatible with the 34*4882a593Smuzhiyun dvi-connector binding. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun required: 37*4882a593Smuzhiyun - port@0 38*4882a593Smuzhiyun - port@1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - ports 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunadditionalProperties: false 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunexamples: 48*4882a593Smuzhiyun - | 49*4882a593Smuzhiyun i2c { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun vga-dvi-encoder@76 { 54*4882a593Smuzhiyun compatible = "chrontel,ch7033"; 55*4882a593Smuzhiyun reg = <0x76>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ports { 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <0>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun port@0 { 62*4882a593Smuzhiyun reg = <0>; 63*4882a593Smuzhiyun endpoint { 64*4882a593Smuzhiyun remote-endpoint = <&lcd0_rgb_out>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun port@1 { 69*4882a593Smuzhiyun reg = <1>; 70*4882a593Smuzhiyun endpoint { 71*4882a593Smuzhiyun remote-endpoint = <&dvi_in>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78