1*4882a593SmuzhiyunARM HDLCD 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a display controller found on several development platforms produced 4*4882a593Smuzhiyunby ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB 5*4882a593Smuzhiyunstreamer that reads the data from a framebuffer and sends it to a single 6*4882a593Smuzhiyundigital encoder (DVI or HDMI). 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun - compatible: "arm,hdlcd" 10*4882a593Smuzhiyun - reg: Physical base address and length of the controller's registers. 11*4882a593Smuzhiyun - interrupts: One interrupt used by the display controller to notify the 12*4882a593Smuzhiyun interrupt controller when any of the interrupt sources programmed in 13*4882a593Smuzhiyun the interrupt mask register have activated. 14*4882a593Smuzhiyun - clocks: A list of phandle + clock-specifier pairs, one for each 15*4882a593Smuzhiyun entry in 'clock-names'. 16*4882a593Smuzhiyun - clock-names: A list of clock names. For HDLCD it should contain: 17*4882a593Smuzhiyun - "pxlclk" for the clock feeding the output PLL of the controller. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRequired sub-nodes: 20*4882a593Smuzhiyun - port: The HDLCD connection to an encoder chip. The connection is modeled 21*4882a593Smuzhiyun using the OF graph bindings specified in 22*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun - memory-region: phandle to a node describing memory (see 26*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be 27*4882a593Smuzhiyun used for the framebuffer; if not present, the framebuffer may be located 28*4882a593Smuzhiyun anywhere in memory. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun/ { 34*4882a593Smuzhiyun ... 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun hdlcd@2b000000 { 37*4882a593Smuzhiyun compatible = "arm,hdlcd"; 38*4882a593Smuzhiyun reg = <0 0x2b000000 0 0x1000>; 39*4882a593Smuzhiyun interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 40*4882a593Smuzhiyun clocks = <&oscclk5>; 41*4882a593Smuzhiyun clock-names = "pxlclk"; 42*4882a593Smuzhiyun port { 43*4882a593Smuzhiyun hdlcd_output: endpoint@0 { 44*4882a593Smuzhiyun remote-endpoint = <&hdmi_enc_input>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* HDMI encoder on I2C bus */ 50*4882a593Smuzhiyun i2c@7ffa0000 { 51*4882a593Smuzhiyun .... 52*4882a593Smuzhiyun hdmi-transmitter@70 { 53*4882a593Smuzhiyun compatible = "....."; 54*4882a593Smuzhiyun reg = <0x70>; 55*4882a593Smuzhiyun port@0 { 56*4882a593Smuzhiyun hdmi_enc_input: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&hdlcd_output>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun hdmi_enc_output: endpoint { 61*4882a593Smuzhiyun remote-endpoint = <&hdmi_1_port>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun hdmi1: connector@1 { 69*4882a593Smuzhiyun compatible = "hdmi-connector"; 70*4882a593Smuzhiyun type = "a"; 71*4882a593Smuzhiyun port { 72*4882a593Smuzhiyun hdmi_1_port: endpoint { 73*4882a593Smuzhiyun remote-endpoint = <&hdmi_enc_output>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun ... 79*4882a593Smuzhiyun}; 80