1*4882a593SmuzhiyunARM Mali-DP 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe following bindings apply to a family of Display Processors sold as 4*4882a593Smuzhiyunlicensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and 5*4882a593SmuzhiyunDP650 processors that offer multiple composition layers, support for 6*4882a593Smuzhiyunrotation and scaling output. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun - compatible: should be one of 10*4882a593Smuzhiyun "arm,mali-dp500" 11*4882a593Smuzhiyun "arm,mali-dp550" 12*4882a593Smuzhiyun "arm,mali-dp650" 13*4882a593Smuzhiyun depending on the particular implementation present in the hardware 14*4882a593Smuzhiyun - reg: Physical base address and size of the block of registers used by 15*4882a593Smuzhiyun the processor. 16*4882a593Smuzhiyun - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt, 17*4882a593Smuzhiyun interrupt client nodes. 18*4882a593Smuzhiyun - interrupt-names: name of the engine inside the processor that will 19*4882a593Smuzhiyun use the corresponding interrupt. Should be one of "DE" or "SE". 20*4882a593Smuzhiyun - clocks: A list of phandle + clock-specifier pairs, one for each entry 21*4882a593Smuzhiyun in 'clock-names' 22*4882a593Smuzhiyun - clock-names: A list of clock names. It should contain: 23*4882a593Smuzhiyun - "pclk": for the APB interface clock 24*4882a593Smuzhiyun - "aclk": for the AXI interface clock 25*4882a593Smuzhiyun - "mclk": for the main processor clock 26*4882a593Smuzhiyun - "pxlclk": for the pixel clock feeding the output PLL of the processor. 27*4882a593Smuzhiyun - arm,malidp-output-port-lines: Array of u8 values describing the number 28*4882a593Smuzhiyun of output lines per channel (R, G and B). 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRequired sub-nodes: 31*4882a593Smuzhiyun - port: The Mali DP connection to an encoder input port. The connection 32*4882a593Smuzhiyun is modelled using the OF graph bindings specified in 33*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties: 36*4882a593Smuzhiyun - memory-region: phandle to a node describing memory (see 37*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) 38*4882a593Smuzhiyun to be used for the framebuffer; if not present, the framebuffer may 39*4882a593Smuzhiyun be located anywhere in memory. 40*4882a593Smuzhiyun - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS 41*4882a593Smuzhiyun levels of DP500's QoS signaling. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunExample: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun/ { 47*4882a593Smuzhiyun ... 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun dp0: malidp@6f200000 { 50*4882a593Smuzhiyun compatible = "arm,mali-dp650"; 51*4882a593Smuzhiyun reg = <0 0x6f200000 0 0x20000>; 52*4882a593Smuzhiyun memory-region = <&display_reserved>; 53*4882a593Smuzhiyun interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>, 54*4882a593Smuzhiyun <0 168 IRQ_TYPE_LEVEL_HIGH>; 55*4882a593Smuzhiyun interrupt-names = "DE", "SE"; 56*4882a593Smuzhiyun clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; 57*4882a593Smuzhiyun clock-names = "pxlclk", "mclk", "aclk", "pclk"; 58*4882a593Smuzhiyun arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 59*4882a593Smuzhiyun arm,malidp-arqos-high-level = <0xd000d000>; 60*4882a593Smuzhiyun port { 61*4882a593Smuzhiyun dp0_output: endpoint { 62*4882a593Smuzhiyun remote-endpoint = <&tda998x_2_input>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun ... 68*4882a593Smuzhiyun}; 69