1*4882a593SmuzhiyunDevice Tree bindings for Arm Komeda display driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "arm,mali-d71" 5*4882a593Smuzhiyun- reg: Physical base address and length of the registers in the system 6*4882a593Smuzhiyun- interrupts: the interrupt line number of the device in the system 7*4882a593Smuzhiyun- clocks: A list of phandle + clock-specifier pairs, one for each entry 8*4882a593Smuzhiyun in 'clock-names' 9*4882a593Smuzhiyun- clock-names: A list of clock names. It should contain: 10*4882a593Smuzhiyun - "aclk": for the main processor clock 11*4882a593Smuzhiyun- #address-cells: Must be 1 12*4882a593Smuzhiyun- #size-cells: Must be 0 13*4882a593Smuzhiyun- iommus: configure the stream id to IOMMU, Must be configured if want to 14*4882a593Smuzhiyun enable iommu in display. for how to configure this node please reference 15*4882a593Smuzhiyun devicetree/bindings/iommu/arm,smmu-v3.txt, 16*4882a593Smuzhiyun devicetree/bindings/iommu/iommu.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties for sub-node: pipeline@nq 19*4882a593SmuzhiyunEach device contains one or two pipeline sub-nodes (at least one), each 20*4882a593Smuzhiyunpipeline node should provide properties: 21*4882a593Smuzhiyun- reg: Zero-indexed identifier for the pipeline 22*4882a593Smuzhiyun- clocks: A list of phandle + clock-specifier pairs, one for each entry 23*4882a593Smuzhiyun in 'clock-names' 24*4882a593Smuzhiyun- clock-names: should contain: 25*4882a593Smuzhiyun - "pxclk": pixel clock 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- port: each pipeline connect to an encoder input port. The connection is 28*4882a593Smuzhiyun modeled using the OF graph bindings specified in 29*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun - memory-region: phandle to a node describing memory (see 33*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) 34*4882a593Smuzhiyun to be used for the framebuffer; if not present, the framebuffer may 35*4882a593Smuzhiyun be located anywhere in memory. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample: 38*4882a593Smuzhiyun/ { 39*4882a593Smuzhiyun ... 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun dp0: display@c00000 { 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <0>; 44*4882a593Smuzhiyun compatible = "arm,mali-d71"; 45*4882a593Smuzhiyun reg = <0xc00000 0x20000>; 46*4882a593Smuzhiyun interrupts = <0 168 4>; 47*4882a593Smuzhiyun clocks = <&dpu_aclk>; 48*4882a593Smuzhiyun clock-names = "aclk"; 49*4882a593Smuzhiyun iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, 50*4882a593Smuzhiyun <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, 51*4882a593Smuzhiyun <&smmu 8>, <&smmu 9>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun dp0_pipe0: pipeline@0 { 54*4882a593Smuzhiyun clocks = <&fpgaosc2>; 55*4882a593Smuzhiyun clock-names = "pxclk"; 56*4882a593Smuzhiyun reg = <0>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun port { 59*4882a593Smuzhiyun dp0_pipe0_out: endpoint { 60*4882a593Smuzhiyun remote-endpoint = <&db_dvi0_in>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun dp0_pipe1: pipeline@1 { 66*4882a593Smuzhiyun clocks = <&fpgaosc2>; 67*4882a593Smuzhiyun clock-names = "pxclk"; 68*4882a593Smuzhiyun reg = <1>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun port { 71*4882a593Smuzhiyun dp0_pipe1_out: endpoint { 72*4882a593Smuzhiyun remote-endpoint = <&db_dvi1_in>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun ... 78*4882a593Smuzhiyun}; 79