1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A83t HDMI PHY Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  "#phy-cells":
15*4882a593Smuzhiyun    const: 0
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    enum:
19*4882a593Smuzhiyun      - allwinner,sun8i-a83t-hdmi-phy
20*4882a593Smuzhiyun      - allwinner,sun8i-h3-hdmi-phy
21*4882a593Smuzhiyun      - allwinner,sun8i-r40-hdmi-phy
22*4882a593Smuzhiyun      - allwinner,sun50i-a64-hdmi-phy
23*4882a593Smuzhiyun      - allwinner,sun50i-h6-hdmi-phy
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  reg:
26*4882a593Smuzhiyun    maxItems: 1
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  clocks:
29*4882a593Smuzhiyun    minItems: 2
30*4882a593Smuzhiyun    maxItems: 4
31*4882a593Smuzhiyun    items:
32*4882a593Smuzhiyun      - description: Bus Clock
33*4882a593Smuzhiyun      - description: Module Clock
34*4882a593Smuzhiyun      - description: Parent of the PHY clock
35*4882a593Smuzhiyun      - description: Second possible parent of the PHY clock
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  clock-names:
38*4882a593Smuzhiyun    minItems: 2
39*4882a593Smuzhiyun    maxItems: 4
40*4882a593Smuzhiyun    items:
41*4882a593Smuzhiyun      - const: bus
42*4882a593Smuzhiyun      - const: mod
43*4882a593Smuzhiyun      - const: pll-0
44*4882a593Smuzhiyun      - const: pll-1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  resets:
47*4882a593Smuzhiyun    maxItems: 1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  reset-names:
50*4882a593Smuzhiyun    const: phy
51*4882a593Smuzhiyun
52*4882a593Smuzhiyunrequired:
53*4882a593Smuzhiyun  - compatible
54*4882a593Smuzhiyun  - reg
55*4882a593Smuzhiyun  - clocks
56*4882a593Smuzhiyun  - clock-names
57*4882a593Smuzhiyun  - resets
58*4882a593Smuzhiyun  - reset-names
59*4882a593Smuzhiyun
60*4882a593Smuzhiyunif:
61*4882a593Smuzhiyun  properties:
62*4882a593Smuzhiyun    compatible:
63*4882a593Smuzhiyun      contains:
64*4882a593Smuzhiyun        enum:
65*4882a593Smuzhiyun          - allwinner,sun8i-r40-hdmi-phy
66*4882a593Smuzhiyun
67*4882a593Smuzhiyunthen:
68*4882a593Smuzhiyun  properties:
69*4882a593Smuzhiyun    clocks:
70*4882a593Smuzhiyun      minItems: 4
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun    clock-names:
73*4882a593Smuzhiyun      minItems: 4
74*4882a593Smuzhiyun
75*4882a593Smuzhiyunelse:
76*4882a593Smuzhiyun  if:
77*4882a593Smuzhiyun    properties:
78*4882a593Smuzhiyun      compatible:
79*4882a593Smuzhiyun        contains:
80*4882a593Smuzhiyun          enum:
81*4882a593Smuzhiyun            - allwinner,sun8i-h3-hdmi-phy
82*4882a593Smuzhiyun            - allwinner,sun50i-a64-hdmi-phy
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun  then:
85*4882a593Smuzhiyun    properties:
86*4882a593Smuzhiyun      clocks:
87*4882a593Smuzhiyun        minItems: 3
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun      clock-names:
90*4882a593Smuzhiyun        minItems: 3
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun  else:
93*4882a593Smuzhiyun    properties:
94*4882a593Smuzhiyun      clocks:
95*4882a593Smuzhiyun        maxItems: 2
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun      clock-names:
98*4882a593Smuzhiyun        maxItems: 2
99*4882a593Smuzhiyun
100*4882a593SmuzhiyunadditionalProperties: false
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunexamples:
103*4882a593Smuzhiyun  - |
104*4882a593Smuzhiyun    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
105*4882a593Smuzhiyun    #include <dt-bindings/reset/sun8i-a83t-ccu.h>
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun    hdmi_phy: hdmi-phy@1ef0000 {
108*4882a593Smuzhiyun        compatible = "allwinner,sun8i-a83t-hdmi-phy";
109*4882a593Smuzhiyun        reg = <0x01ef0000 0x10000>;
110*4882a593Smuzhiyun        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
111*4882a593Smuzhiyun        clock-names = "bus", "mod";
112*4882a593Smuzhiyun        resets = <&ccu RST_BUS_HDMI0>;
113*4882a593Smuzhiyun        reset-names = "phy";
114*4882a593Smuzhiyun        #phy-cells = <0>;
115*4882a593Smuzhiyun    };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun...
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