1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner Display Engine 2.0 Mixer Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  compatible:
15*4882a593Smuzhiyun    enum:
16*4882a593Smuzhiyun      - allwinner,sun8i-a83t-de2-mixer-0
17*4882a593Smuzhiyun      - allwinner,sun8i-a83t-de2-mixer-1
18*4882a593Smuzhiyun      - allwinner,sun8i-h3-de2-mixer-0
19*4882a593Smuzhiyun      - allwinner,sun8i-r40-de2-mixer-0
20*4882a593Smuzhiyun      - allwinner,sun8i-r40-de2-mixer-1
21*4882a593Smuzhiyun      - allwinner,sun8i-v3s-de2-mixer
22*4882a593Smuzhiyun      - allwinner,sun50i-a64-de2-mixer-0
23*4882a593Smuzhiyun      - allwinner,sun50i-a64-de2-mixer-1
24*4882a593Smuzhiyun      - allwinner,sun50i-h6-de3-mixer-0
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  reg:
27*4882a593Smuzhiyun    maxItems: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  clocks:
30*4882a593Smuzhiyun    items:
31*4882a593Smuzhiyun      - description: The mixer interface clock
32*4882a593Smuzhiyun      - description: The mixer module clock
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  clock-names:
35*4882a593Smuzhiyun    items:
36*4882a593Smuzhiyun      - const: bus
37*4882a593Smuzhiyun      - const: mod
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  iommus:
40*4882a593Smuzhiyun    maxItems: 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  resets:
43*4882a593Smuzhiyun    maxItems: 1
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  ports:
46*4882a593Smuzhiyun    type: object
47*4882a593Smuzhiyun    description: |
48*4882a593Smuzhiyun      A ports node with endpoint definitions as defined in
49*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt.
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun    properties:
52*4882a593Smuzhiyun      "#address-cells":
53*4882a593Smuzhiyun        const: 1
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun      "#size-cells":
56*4882a593Smuzhiyun        const: 0
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun      port@0:
59*4882a593Smuzhiyun        type: object
60*4882a593Smuzhiyun        description: |
61*4882a593Smuzhiyun          Input endpoints of the controller.
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun      port@1:
64*4882a593Smuzhiyun        type: object
65*4882a593Smuzhiyun        description: |
66*4882a593Smuzhiyun          Output endpoints of the controller.
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun    required:
69*4882a593Smuzhiyun      - "#address-cells"
70*4882a593Smuzhiyun      - "#size-cells"
71*4882a593Smuzhiyun      - port@1
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun    additionalProperties: false
74*4882a593Smuzhiyun
75*4882a593Smuzhiyunrequired:
76*4882a593Smuzhiyun  - compatible
77*4882a593Smuzhiyun  - reg
78*4882a593Smuzhiyun  - clocks
79*4882a593Smuzhiyun  - clock-names
80*4882a593Smuzhiyun  - resets
81*4882a593Smuzhiyun  - ports
82*4882a593Smuzhiyun
83*4882a593SmuzhiyunadditionalProperties: false
84*4882a593Smuzhiyun
85*4882a593Smuzhiyunexamples:
86*4882a593Smuzhiyun  - |
87*4882a593Smuzhiyun    #include <dt-bindings/clock/sun8i-de2.h>
88*4882a593Smuzhiyun    #include <dt-bindings/reset/sun8i-de2.h>
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun    mixer0: mixer@1100000 {
91*4882a593Smuzhiyun        compatible = "allwinner,sun8i-a83t-de2-mixer-0";
92*4882a593Smuzhiyun        reg = <0x01100000 0x100000>;
93*4882a593Smuzhiyun        clocks = <&display_clocks CLK_BUS_MIXER0>,
94*4882a593Smuzhiyun                 <&display_clocks CLK_MIXER0>;
95*4882a593Smuzhiyun        clock-names = "bus",
96*4882a593Smuzhiyun                      "mod";
97*4882a593Smuzhiyun        resets = <&display_clocks RST_MIXER0>;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun        ports {
100*4882a593Smuzhiyun            #address-cells = <1>;
101*4882a593Smuzhiyun            #size-cells = <0>;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun            mixer0_out: port@1 {
104*4882a593Smuzhiyun                #address-cells = <1>;
105*4882a593Smuzhiyun                #size-cells = <0>;
106*4882a593Smuzhiyun                reg = <1>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun                mixer0_out_tcon0: endpoint@0 {
109*4882a593Smuzhiyun                    reg = <0>;
110*4882a593Smuzhiyun                    remote-endpoint = <&tcon0_in_mixer0>;
111*4882a593Smuzhiyun                };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun                mixer0_out_tcon1: endpoint@1 {
114*4882a593Smuzhiyun                    reg = <1>;
115*4882a593Smuzhiyun                    remote-endpoint = <&tcon1_in_mixer0>;
116*4882a593Smuzhiyun                };
117*4882a593Smuzhiyun            };
118*4882a593Smuzhiyun        };
119*4882a593Smuzhiyun    };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun...
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