xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A31 Dynamic Range Controller Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The DRC (Dynamic Range Controller) allows to dynamically adjust
15*4882a593Smuzhiyun  pixel brightness/contrast based on histogram measurements for LCD
16*4882a593Smuzhiyun  content adaptive backlight control.
17*4882a593Smuzhiyun
18*4882a593Smuzhiyunproperties:
19*4882a593Smuzhiyun  compatible:
20*4882a593Smuzhiyun    enum:
21*4882a593Smuzhiyun      - allwinner,sun6i-a31-drc
22*4882a593Smuzhiyun      - allwinner,sun6i-a31s-drc
23*4882a593Smuzhiyun      - allwinner,sun8i-a23-drc
24*4882a593Smuzhiyun      - allwinner,sun8i-a33-drc
25*4882a593Smuzhiyun      - allwinner,sun9i-a80-drc
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  reg:
28*4882a593Smuzhiyun    maxItems: 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  interrupts:
31*4882a593Smuzhiyun    maxItems: 1
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  clocks:
34*4882a593Smuzhiyun    items:
35*4882a593Smuzhiyun      - description: The DRC interface clock
36*4882a593Smuzhiyun      - description: The DRC module clock
37*4882a593Smuzhiyun      - description: The DRC DRAM clock
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  clock-names:
40*4882a593Smuzhiyun    items:
41*4882a593Smuzhiyun      - const: ahb
42*4882a593Smuzhiyun      - const: mod
43*4882a593Smuzhiyun      - const: ram
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  resets:
46*4882a593Smuzhiyun    maxItems: 1
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun  ports:
49*4882a593Smuzhiyun    type: object
50*4882a593Smuzhiyun    description: |
51*4882a593Smuzhiyun      A ports node with endpoint definitions as defined in
52*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt.
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun    properties:
55*4882a593Smuzhiyun      "#address-cells":
56*4882a593Smuzhiyun        const: 1
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun      "#size-cells":
59*4882a593Smuzhiyun        const: 0
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun      port@0:
62*4882a593Smuzhiyun        type: object
63*4882a593Smuzhiyun        description: |
64*4882a593Smuzhiyun          Input endpoints of the controller.
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun      port@1:
67*4882a593Smuzhiyun        type: object
68*4882a593Smuzhiyun        description: |
69*4882a593Smuzhiyun          Output endpoints of the controller.
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun    required:
72*4882a593Smuzhiyun      - "#address-cells"
73*4882a593Smuzhiyun      - "#size-cells"
74*4882a593Smuzhiyun      - port@0
75*4882a593Smuzhiyun      - port@1
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun    additionalProperties: false
78*4882a593Smuzhiyun
79*4882a593Smuzhiyunrequired:
80*4882a593Smuzhiyun  - compatible
81*4882a593Smuzhiyun  - reg
82*4882a593Smuzhiyun  - interrupts
83*4882a593Smuzhiyun  - clocks
84*4882a593Smuzhiyun  - clock-names
85*4882a593Smuzhiyun  - resets
86*4882a593Smuzhiyun  - ports
87*4882a593Smuzhiyun
88*4882a593SmuzhiyunadditionalProperties: false
89*4882a593Smuzhiyun
90*4882a593Smuzhiyunexamples:
91*4882a593Smuzhiyun  - |
92*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun    #include <dt-bindings/clock/sun6i-a31-ccu.h>
95*4882a593Smuzhiyun    #include <dt-bindings/reset/sun6i-a31-ccu.h>
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun    drc0: drc@1e70000 {
98*4882a593Smuzhiyun        compatible = "allwinner,sun6i-a31-drc";
99*4882a593Smuzhiyun        reg = <0x01e70000 0x10000>;
100*4882a593Smuzhiyun        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
101*4882a593Smuzhiyun        clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
102*4882a593Smuzhiyun                 <&ccu CLK_DRAM_DRC0>;
103*4882a593Smuzhiyun        clock-names = "ahb", "mod",
104*4882a593Smuzhiyun                      "ram";
105*4882a593Smuzhiyun        resets = <&ccu RST_AHB1_DRC0>;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun        ports {
108*4882a593Smuzhiyun            #address-cells = <1>;
109*4882a593Smuzhiyun            #size-cells = <0>;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun            drc0_in: port@0 {
112*4882a593Smuzhiyun                reg = <0>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun                drc0_in_be0: endpoint {
115*4882a593Smuzhiyun                    remote-endpoint = <&be0_out_drc0>;
116*4882a593Smuzhiyun                };
117*4882a593Smuzhiyun            };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun            drc0_out: port@1 {
120*4882a593Smuzhiyun                #address-cells = <1>;
121*4882a593Smuzhiyun                #size-cells = <0>;
122*4882a593Smuzhiyun                reg = <1>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun                drc0_out_tcon0: endpoint@0 {
125*4882a593Smuzhiyun                    reg = <0>;
126*4882a593Smuzhiyun                    remote-endpoint = <&tcon0_in_drc0>;
127*4882a593Smuzhiyun                };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun                drc0_out_tcon1: endpoint@1 {
130*4882a593Smuzhiyun                    reg = <1>;
131*4882a593Smuzhiyun                    remote-endpoint = <&tcon1_in_drc0>;
132*4882a593Smuzhiyun                };
133*4882a593Smuzhiyun            };
134*4882a593Smuzhiyun        };
135*4882a593Smuzhiyun    };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun...
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