1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 Timings Controller (TCON) Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The TCON acts as a timing controller for RGB, LVDS and TV 15*4882a593Smuzhiyun interfaces. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun "#clock-cells": 19*4882a593Smuzhiyun const: 0 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun oneOf: 23*4882a593Smuzhiyun - const: allwinner,sun4i-a10-tcon 24*4882a593Smuzhiyun - const: allwinner,sun5i-a13-tcon 25*4882a593Smuzhiyun - const: allwinner,sun6i-a31-tcon 26*4882a593Smuzhiyun - const: allwinner,sun6i-a31s-tcon 27*4882a593Smuzhiyun - const: allwinner,sun7i-a20-tcon 28*4882a593Smuzhiyun - const: allwinner,sun8i-a23-tcon 29*4882a593Smuzhiyun - const: allwinner,sun8i-a33-tcon 30*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-tcon-lcd 31*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-tcon-tv 32*4882a593Smuzhiyun - const: allwinner,sun8i-r40-tcon-tv 33*4882a593Smuzhiyun - const: allwinner,sun8i-v3s-tcon 34*4882a593Smuzhiyun - const: allwinner,sun9i-a80-tcon-lcd 35*4882a593Smuzhiyun - const: allwinner,sun9i-a80-tcon-tv 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun - items: 38*4882a593Smuzhiyun - enum: 39*4882a593Smuzhiyun - allwinner,sun7i-a20-tcon0 40*4882a593Smuzhiyun - allwinner,sun7i-a20-tcon1 41*4882a593Smuzhiyun - const: allwinner,sun7i-a20-tcon 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun - items: 44*4882a593Smuzhiyun - enum: 45*4882a593Smuzhiyun - allwinner,sun50i-a64-tcon-lcd 46*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-tcon-lcd 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun - items: 49*4882a593Smuzhiyun - enum: 50*4882a593Smuzhiyun - allwinner,sun8i-h3-tcon-tv 51*4882a593Smuzhiyun - allwinner,sun50i-a64-tcon-tv 52*4882a593Smuzhiyun - const: allwinner,sun8i-a83t-tcon-tv 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun - items: 55*4882a593Smuzhiyun - enum: 56*4882a593Smuzhiyun - allwinner,sun50i-h6-tcon-tv 57*4882a593Smuzhiyun - const: allwinner,sun8i-r40-tcon-tv 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun reg: 60*4882a593Smuzhiyun maxItems: 1 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun interrupts: 63*4882a593Smuzhiyun maxItems: 1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun clocks: 66*4882a593Smuzhiyun minItems: 1 67*4882a593Smuzhiyun maxItems: 4 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun clock-names: 70*4882a593Smuzhiyun minItems: 1 71*4882a593Smuzhiyun maxItems: 4 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun clock-output-names: 74*4882a593Smuzhiyun description: 75*4882a593Smuzhiyun Name of the LCD pixel clock created. 76*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/string-array 77*4882a593Smuzhiyun maxItems: 1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun dmas: 80*4882a593Smuzhiyun maxItems: 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun resets: 83*4882a593Smuzhiyun anyOf: 84*4882a593Smuzhiyun - items: 85*4882a593Smuzhiyun - description: TCON Reset Line 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun - items: 88*4882a593Smuzhiyun - description: TCON Reset Line 89*4882a593Smuzhiyun - description: TCON LVDS Reset Line 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun - items: 92*4882a593Smuzhiyun - description: TCON Reset Line 93*4882a593Smuzhiyun - description: TCON eDP Reset Line 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun - items: 96*4882a593Smuzhiyun - description: TCON Reset Line 97*4882a593Smuzhiyun - description: TCON eDP Reset Line 98*4882a593Smuzhiyun - description: TCON LVDS Reset Line 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun reset-names: 101*4882a593Smuzhiyun oneOf: 102*4882a593Smuzhiyun - const: lcd 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun - items: 105*4882a593Smuzhiyun - const: lcd 106*4882a593Smuzhiyun - const: lvds 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun - items: 109*4882a593Smuzhiyun - const: lcd 110*4882a593Smuzhiyun - const: edp 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun - items: 113*4882a593Smuzhiyun - const: lcd 114*4882a593Smuzhiyun - const: edp 115*4882a593Smuzhiyun - const: lvds 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun ports: 118*4882a593Smuzhiyun type: object 119*4882a593Smuzhiyun description: | 120*4882a593Smuzhiyun A ports node with endpoint definitions as defined in 121*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun properties: 124*4882a593Smuzhiyun "#address-cells": 125*4882a593Smuzhiyun const: 1 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun "#size-cells": 128*4882a593Smuzhiyun const: 0 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun port@0: 131*4882a593Smuzhiyun type: object 132*4882a593Smuzhiyun description: | 133*4882a593Smuzhiyun Input endpoints of the controller. 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun port@1: 136*4882a593Smuzhiyun type: object 137*4882a593Smuzhiyun description: | 138*4882a593Smuzhiyun Output endpoints of the controller. 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun patternProperties: 141*4882a593Smuzhiyun "^endpoint(@[0-9])$": 142*4882a593Smuzhiyun type: object 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun properties: 145*4882a593Smuzhiyun allwinner,tcon-channel: 146*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 147*4882a593Smuzhiyun description: | 148*4882a593Smuzhiyun TCON can have 1 or 2 channels, usually with the 149*4882a593Smuzhiyun first channel being used for the panels interfaces 150*4882a593Smuzhiyun (RGB, LVDS, etc.), and the second being used for the 151*4882a593Smuzhiyun outputs that require another controller (TV Encoder, 152*4882a593Smuzhiyun HDMI, etc.). 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun If that property is present, specifies the TCON 155*4882a593Smuzhiyun channel the endpoint is associated to. If that 156*4882a593Smuzhiyun property is not present, the endpoint number will be 157*4882a593Smuzhiyun used as the channel number. 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun unevaluatedProperties: true 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun required: 162*4882a593Smuzhiyun - "#address-cells" 163*4882a593Smuzhiyun - "#size-cells" 164*4882a593Smuzhiyun - port@0 165*4882a593Smuzhiyun - port@1 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun additionalProperties: false 168*4882a593Smuzhiyun 169*4882a593Smuzhiyunrequired: 170*4882a593Smuzhiyun - compatible 171*4882a593Smuzhiyun - reg 172*4882a593Smuzhiyun - interrupts 173*4882a593Smuzhiyun - clocks 174*4882a593Smuzhiyun - clock-names 175*4882a593Smuzhiyun - resets 176*4882a593Smuzhiyun - ports 177*4882a593Smuzhiyun 178*4882a593SmuzhiyunadditionalProperties: false 179*4882a593Smuzhiyun 180*4882a593SmuzhiyunallOf: 181*4882a593Smuzhiyun - if: 182*4882a593Smuzhiyun properties: 183*4882a593Smuzhiyun compatible: 184*4882a593Smuzhiyun contains: 185*4882a593Smuzhiyun enum: 186*4882a593Smuzhiyun - allwinner,sun4i-a10-tcon 187*4882a593Smuzhiyun - allwinner,sun5i-a13-tcon 188*4882a593Smuzhiyun - allwinner,sun7i-a20-tcon 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun then: 191*4882a593Smuzhiyun properties: 192*4882a593Smuzhiyun clocks: 193*4882a593Smuzhiyun minItems: 3 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun clock-names: 196*4882a593Smuzhiyun items: 197*4882a593Smuzhiyun - const: ahb 198*4882a593Smuzhiyun - const: tcon-ch0 199*4882a593Smuzhiyun - const: tcon-ch1 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun - if: 202*4882a593Smuzhiyun properties: 203*4882a593Smuzhiyun compatible: 204*4882a593Smuzhiyun contains: 205*4882a593Smuzhiyun enum: 206*4882a593Smuzhiyun - allwinner,sun6i-a31-tcon 207*4882a593Smuzhiyun - allwinner,sun6i-a31s-tcon 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun then: 210*4882a593Smuzhiyun properties: 211*4882a593Smuzhiyun clocks: 212*4882a593Smuzhiyun minItems: 4 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun clock-names: 215*4882a593Smuzhiyun items: 216*4882a593Smuzhiyun - const: ahb 217*4882a593Smuzhiyun - const: tcon-ch0 218*4882a593Smuzhiyun - const: tcon-ch1 219*4882a593Smuzhiyun - const: lvds-alt 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun - if: 222*4882a593Smuzhiyun properties: 223*4882a593Smuzhiyun compatible: 224*4882a593Smuzhiyun contains: 225*4882a593Smuzhiyun enum: 226*4882a593Smuzhiyun - allwinner,sun8i-a23-tcon 227*4882a593Smuzhiyun - allwinner,sun8i-a33-tcon 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun then: 230*4882a593Smuzhiyun properties: 231*4882a593Smuzhiyun clocks: 232*4882a593Smuzhiyun minItems: 3 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun clock-names: 235*4882a593Smuzhiyun items: 236*4882a593Smuzhiyun - const: ahb 237*4882a593Smuzhiyun - const: tcon-ch0 238*4882a593Smuzhiyun - const: lvds-alt 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun - if: 241*4882a593Smuzhiyun properties: 242*4882a593Smuzhiyun compatible: 243*4882a593Smuzhiyun contains: 244*4882a593Smuzhiyun enum: 245*4882a593Smuzhiyun - allwinner,sun8i-a83t-tcon-lcd 246*4882a593Smuzhiyun - allwinner,sun8i-v3s-tcon 247*4882a593Smuzhiyun - allwinner,sun9i-a80-tcon-lcd 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun then: 250*4882a593Smuzhiyun properties: 251*4882a593Smuzhiyun clocks: 252*4882a593Smuzhiyun minItems: 2 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun clock-names: 255*4882a593Smuzhiyun items: 256*4882a593Smuzhiyun - const: ahb 257*4882a593Smuzhiyun - const: tcon-ch0 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun - if: 260*4882a593Smuzhiyun properties: 261*4882a593Smuzhiyun compatible: 262*4882a593Smuzhiyun contains: 263*4882a593Smuzhiyun enum: 264*4882a593Smuzhiyun - allwinner,sun8i-a83t-tcon-tv 265*4882a593Smuzhiyun - allwinner,sun8i-r40-tcon-tv 266*4882a593Smuzhiyun - allwinner,sun9i-a80-tcon-tv 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun then: 269*4882a593Smuzhiyun properties: 270*4882a593Smuzhiyun clocks: 271*4882a593Smuzhiyun minItems: 2 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun clock-names: 274*4882a593Smuzhiyun items: 275*4882a593Smuzhiyun - const: ahb 276*4882a593Smuzhiyun - const: tcon-ch1 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun - if: 279*4882a593Smuzhiyun properties: 280*4882a593Smuzhiyun compatible: 281*4882a593Smuzhiyun contains: 282*4882a593Smuzhiyun enum: 283*4882a593Smuzhiyun - allwinner,sun5i-a13-tcon 284*4882a593Smuzhiyun - allwinner,sun6i-a31-tcon 285*4882a593Smuzhiyun - allwinner,sun6i-a31s-tcon 286*4882a593Smuzhiyun - allwinner,sun7i-a20-tcon 287*4882a593Smuzhiyun - allwinner,sun8i-a23-tcon 288*4882a593Smuzhiyun - allwinner,sun8i-a33-tcon 289*4882a593Smuzhiyun - allwinner,sun8i-v3s-tcon 290*4882a593Smuzhiyun - allwinner,sun9i-a80-tcon-lcd 291*4882a593Smuzhiyun - allwinner,sun4i-a10-tcon 292*4882a593Smuzhiyun - allwinner,sun8i-a83t-tcon-lcd 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun then: 295*4882a593Smuzhiyun required: 296*4882a593Smuzhiyun - "#clock-cells" 297*4882a593Smuzhiyun - clock-output-names 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun - if: 300*4882a593Smuzhiyun properties: 301*4882a593Smuzhiyun compatible: 302*4882a593Smuzhiyun contains: 303*4882a593Smuzhiyun enum: 304*4882a593Smuzhiyun - allwinner,sun6i-a31-tcon 305*4882a593Smuzhiyun - allwinner,sun6i-a31s-tcon 306*4882a593Smuzhiyun - allwinner,sun8i-a23-tcon 307*4882a593Smuzhiyun - allwinner,sun8i-a33-tcon 308*4882a593Smuzhiyun - allwinner,sun8i-a83t-tcon-lcd 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun then: 311*4882a593Smuzhiyun properties: 312*4882a593Smuzhiyun resets: 313*4882a593Smuzhiyun minItems: 2 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun reset-names: 316*4882a593Smuzhiyun items: 317*4882a593Smuzhiyun - const: lcd 318*4882a593Smuzhiyun - const: lvds 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun - if: 321*4882a593Smuzhiyun properties: 322*4882a593Smuzhiyun compatible: 323*4882a593Smuzhiyun contains: 324*4882a593Smuzhiyun enum: 325*4882a593Smuzhiyun - allwinner,sun9i-a80-tcon-lcd 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun then: 328*4882a593Smuzhiyun properties: 329*4882a593Smuzhiyun resets: 330*4882a593Smuzhiyun minItems: 3 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun reset-names: 333*4882a593Smuzhiyun items: 334*4882a593Smuzhiyun - const: lcd 335*4882a593Smuzhiyun - const: edp 336*4882a593Smuzhiyun - const: lvds 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun - if: 339*4882a593Smuzhiyun properties: 340*4882a593Smuzhiyun compatible: 341*4882a593Smuzhiyun contains: 342*4882a593Smuzhiyun enum: 343*4882a593Smuzhiyun - allwinner,sun9i-a80-tcon-tv 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun then: 346*4882a593Smuzhiyun properties: 347*4882a593Smuzhiyun resets: 348*4882a593Smuzhiyun minItems: 2 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun reset-names: 351*4882a593Smuzhiyun items: 352*4882a593Smuzhiyun - const: lcd 353*4882a593Smuzhiyun - const: edp 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun - if: 356*4882a593Smuzhiyun properties: 357*4882a593Smuzhiyun compatible: 358*4882a593Smuzhiyun contains: 359*4882a593Smuzhiyun enum: 360*4882a593Smuzhiyun - allwinner,sun4i-a10-tcon 361*4882a593Smuzhiyun - allwinner,sun5i-a13-tcon 362*4882a593Smuzhiyun - allwinner,sun6i-a31-tcon 363*4882a593Smuzhiyun - allwinner,sun6i-a31s-tcon 364*4882a593Smuzhiyun - allwinner,sun7i-a20-tcon 365*4882a593Smuzhiyun - allwinner,sun8i-a23-tcon 366*4882a593Smuzhiyun - allwinner,sun8i-a33-tcon 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun then: 369*4882a593Smuzhiyun required: 370*4882a593Smuzhiyun - dmas 371*4882a593Smuzhiyun 372*4882a593Smuzhiyunexamples: 373*4882a593Smuzhiyun - | 374*4882a593Smuzhiyun #include <dt-bindings/dma/sun4i-a10.h> 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* 377*4882a593Smuzhiyun * This comes from the clock/sun4i-a10-ccu.h and 378*4882a593Smuzhiyun * reset/sun4i-a10-ccu.h headers, but we can't include them since 379*4882a593Smuzhiyun * it would trigger a bunch of warnings for redefinitions of 380*4882a593Smuzhiyun * symbols with the other example. 381*4882a593Smuzhiyun */ 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun #define CLK_AHB_LCD0 56 384*4882a593Smuzhiyun #define CLK_TCON0_CH0 149 385*4882a593Smuzhiyun #define CLK_TCON0_CH1 155 386*4882a593Smuzhiyun #define RST_TCON0 11 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun lcd-controller@1c0c000 { 389*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-tcon"; 390*4882a593Smuzhiyun reg = <0x01c0c000 0x1000>; 391*4882a593Smuzhiyun interrupts = <44>; 392*4882a593Smuzhiyun resets = <&ccu RST_TCON0>; 393*4882a593Smuzhiyun reset-names = "lcd"; 394*4882a593Smuzhiyun clocks = <&ccu CLK_AHB_LCD0>, 395*4882a593Smuzhiyun <&ccu CLK_TCON0_CH0>, 396*4882a593Smuzhiyun <&ccu CLK_TCON0_CH1>; 397*4882a593Smuzhiyun clock-names = "ahb", 398*4882a593Smuzhiyun "tcon-ch0", 399*4882a593Smuzhiyun "tcon-ch1"; 400*4882a593Smuzhiyun clock-output-names = "tcon0-pixel-clock"; 401*4882a593Smuzhiyun #clock-cells = <0>; 402*4882a593Smuzhiyun dmas = <&dma SUN4I_DMA_DEDICATED 14>; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun ports { 405*4882a593Smuzhiyun #address-cells = <1>; 406*4882a593Smuzhiyun #size-cells = <0>; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun port@0 { 409*4882a593Smuzhiyun #address-cells = <1>; 410*4882a593Smuzhiyun #size-cells = <0>; 411*4882a593Smuzhiyun reg = <0>; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun endpoint@0 { 414*4882a593Smuzhiyun reg = <0>; 415*4882a593Smuzhiyun remote-endpoint = <&be0_out_tcon0>; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun endpoint@1 { 419*4882a593Smuzhiyun reg = <1>; 420*4882a593Smuzhiyun remote-endpoint = <&be1_out_tcon0>; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun port@1 { 425*4882a593Smuzhiyun #address-cells = <1>; 426*4882a593Smuzhiyun #size-cells = <0>; 427*4882a593Smuzhiyun reg = <1>; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun endpoint@1 { 430*4882a593Smuzhiyun reg = <1>; 431*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_tcon0>; 432*4882a593Smuzhiyun allwinner,tcon-channel = <1>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun #undef CLK_AHB_LCD0 439*4882a593Smuzhiyun #undef CLK_TCON0_CH0 440*4882a593Smuzhiyun #undef CLK_TCON0_CH1 441*4882a593Smuzhiyun #undef RST_TCON0 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun - | 444*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun /* 447*4882a593Smuzhiyun * This comes from the clock/sun6i-a31-ccu.h and 448*4882a593Smuzhiyun * reset/sun6i-a31-ccu.h headers, but we can't include them since 449*4882a593Smuzhiyun * it would trigger a bunch of warnings for redefinitions of 450*4882a593Smuzhiyun * symbols with the other example. 451*4882a593Smuzhiyun */ 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun #define CLK_PLL_MIPI 15 454*4882a593Smuzhiyun #define CLK_AHB1_LCD0 47 455*4882a593Smuzhiyun #define CLK_LCD0_CH0 127 456*4882a593Smuzhiyun #define CLK_LCD0_CH1 129 457*4882a593Smuzhiyun #define RST_AHB1_LCD0 27 458*4882a593Smuzhiyun #define RST_AHB1_LVDS 41 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun lcd-controller@1c0c000 { 461*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-tcon"; 462*4882a593Smuzhiyun reg = <0x01c0c000 0x1000>; 463*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 464*4882a593Smuzhiyun dmas = <&dma 11>; 465*4882a593Smuzhiyun resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>; 466*4882a593Smuzhiyun reset-names = "lcd", "lvds"; 467*4882a593Smuzhiyun clocks = <&ccu CLK_AHB1_LCD0>, 468*4882a593Smuzhiyun <&ccu CLK_LCD0_CH0>, 469*4882a593Smuzhiyun <&ccu CLK_LCD0_CH1>, 470*4882a593Smuzhiyun <&ccu CLK_PLL_MIPI>; 471*4882a593Smuzhiyun clock-names = "ahb", 472*4882a593Smuzhiyun "tcon-ch0", 473*4882a593Smuzhiyun "tcon-ch1", 474*4882a593Smuzhiyun "lvds-alt"; 475*4882a593Smuzhiyun clock-output-names = "tcon0-pixel-clock"; 476*4882a593Smuzhiyun #clock-cells = <0>; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun ports { 479*4882a593Smuzhiyun #address-cells = <1>; 480*4882a593Smuzhiyun #size-cells = <0>; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun port@0 { 483*4882a593Smuzhiyun #address-cells = <1>; 484*4882a593Smuzhiyun #size-cells = <0>; 485*4882a593Smuzhiyun reg = <0>; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun endpoint@0 { 488*4882a593Smuzhiyun reg = <0>; 489*4882a593Smuzhiyun remote-endpoint = <&drc0_out_tcon0>; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun endpoint@1 { 493*4882a593Smuzhiyun reg = <1>; 494*4882a593Smuzhiyun remote-endpoint = <&drc1_out_tcon0>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun port@1 { 499*4882a593Smuzhiyun #address-cells = <1>; 500*4882a593Smuzhiyun #size-cells = <0>; 501*4882a593Smuzhiyun reg = <1>; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun endpoint@1 { 504*4882a593Smuzhiyun reg = <1>; 505*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_tcon0>; 506*4882a593Smuzhiyun allwinner,tcon-channel = <1>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun #undef CLK_PLL_MIPI 513*4882a593Smuzhiyun #undef CLK_AHB1_LCD0 514*4882a593Smuzhiyun #undef CLK_LCD0_CH0 515*4882a593Smuzhiyun #undef CLK_LCD0_CH1 516*4882a593Smuzhiyun #undef RST_AHB1_LCD0 517*4882a593Smuzhiyun #undef RST_AHB1_LVDS 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun - | 520*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun /* 523*4882a593Smuzhiyun * This comes from the clock/sun9i-a80-ccu.h and 524*4882a593Smuzhiyun * reset/sun9i-a80-ccu.h headers, but we can't include them since 525*4882a593Smuzhiyun * it would trigger a bunch of warnings for redefinitions of 526*4882a593Smuzhiyun * symbols with the other example. 527*4882a593Smuzhiyun */ 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun #define CLK_BUS_LCD0 102 530*4882a593Smuzhiyun #define CLK_LCD0 58 531*4882a593Smuzhiyun #define RST_BUS_LCD0 22 532*4882a593Smuzhiyun #define RST_BUS_EDP 24 533*4882a593Smuzhiyun #define RST_BUS_LVDS 25 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun lcd-controller@3c00000 { 536*4882a593Smuzhiyun compatible = "allwinner,sun9i-a80-tcon-lcd"; 537*4882a593Smuzhiyun reg = <0x03c00000 0x10000>; 538*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 539*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; 540*4882a593Smuzhiyun clock-names = "ahb", "tcon-ch0"; 541*4882a593Smuzhiyun resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>; 542*4882a593Smuzhiyun reset-names = "lcd", "edp", "lvds"; 543*4882a593Smuzhiyun clock-output-names = "tcon0-pixel-clock"; 544*4882a593Smuzhiyun #clock-cells = <0>; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun ports { 547*4882a593Smuzhiyun #address-cells = <1>; 548*4882a593Smuzhiyun #size-cells = <0>; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun port@0 { 551*4882a593Smuzhiyun reg = <0>; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun endpoint { 554*4882a593Smuzhiyun remote-endpoint = <&drc0_out_tcon0>; 555*4882a593Smuzhiyun }; 556*4882a593Smuzhiyun }; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun port@1 { 559*4882a593Smuzhiyun reg = <1>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun }; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun #undef CLK_BUS_TCON0 565*4882a593Smuzhiyun #undef CLK_TCON0 566*4882a593Smuzhiyun #undef RST_BUS_TCON0 567*4882a593Smuzhiyun #undef RST_BUS_EDP 568*4882a593Smuzhiyun #undef RST_BUS_LVDS 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun - | 571*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun /* 574*4882a593Smuzhiyun * This comes from the clock/sun8i-a83t-ccu.h and 575*4882a593Smuzhiyun * reset/sun8i-a83t-ccu.h headers, but we can't include them since 576*4882a593Smuzhiyun * it would trigger a bunch of warnings for redefinitions of 577*4882a593Smuzhiyun * symbols with the other example. 578*4882a593Smuzhiyun */ 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun #define CLK_BUS_TCON0 36 581*4882a593Smuzhiyun #define CLK_TCON0 85 582*4882a593Smuzhiyun #define RST_BUS_TCON0 22 583*4882a593Smuzhiyun #define RST_BUS_LVDS 31 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun lcd-controller@1c0c000 { 586*4882a593Smuzhiyun compatible = "allwinner,sun8i-a83t-tcon-lcd"; 587*4882a593Smuzhiyun reg = <0x01c0c000 0x1000>; 588*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 589*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 590*4882a593Smuzhiyun clock-names = "ahb", "tcon-ch0"; 591*4882a593Smuzhiyun clock-output-names = "tcon-pixel-clock"; 592*4882a593Smuzhiyun #clock-cells = <0>; 593*4882a593Smuzhiyun resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 594*4882a593Smuzhiyun reset-names = "lcd", "lvds"; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun ports { 597*4882a593Smuzhiyun #address-cells = <1>; 598*4882a593Smuzhiyun #size-cells = <0>; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun port@0 { 601*4882a593Smuzhiyun #address-cells = <1>; 602*4882a593Smuzhiyun #size-cells = <0>; 603*4882a593Smuzhiyun reg = <0>; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun endpoint@0 { 606*4882a593Smuzhiyun reg = <0>; 607*4882a593Smuzhiyun remote-endpoint = <&mixer0_out_tcon0>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun endpoint@1 { 611*4882a593Smuzhiyun reg = <1>; 612*4882a593Smuzhiyun remote-endpoint = <&mixer1_out_tcon0>; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun port@1 { 617*4882a593Smuzhiyun reg = <1>; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun #undef CLK_BUS_TCON0 623*4882a593Smuzhiyun #undef CLK_TCON0 624*4882a593Smuzhiyun #undef RST_BUS_TCON0 625*4882a593Smuzhiyun #undef RST_BUS_LVDS 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun - | 628*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun /* 631*4882a593Smuzhiyun * This comes from the clock/sun8i-r40-ccu.h and 632*4882a593Smuzhiyun * reset/sun8i-r40-ccu.h headers, but we can't include them since 633*4882a593Smuzhiyun * it would trigger a bunch of warnings for redefinitions of 634*4882a593Smuzhiyun * symbols with the other example. 635*4882a593Smuzhiyun */ 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun #define CLK_BUS_TCON_TV0 73 638*4882a593Smuzhiyun #define RST_BUS_TCON_TV0 49 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun tcon_tv0: lcd-controller@1c73000 { 641*4882a593Smuzhiyun compatible = "allwinner,sun8i-r40-tcon-tv"; 642*4882a593Smuzhiyun reg = <0x01c73000 0x1000>; 643*4882a593Smuzhiyun interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 644*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; 645*4882a593Smuzhiyun clock-names = "ahb", "tcon-ch1"; 646*4882a593Smuzhiyun resets = <&ccu RST_BUS_TCON_TV0>; 647*4882a593Smuzhiyun reset-names = "lcd"; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun ports { 650*4882a593Smuzhiyun #address-cells = <1>; 651*4882a593Smuzhiyun #size-cells = <0>; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun port@0 { 654*4882a593Smuzhiyun #address-cells = <1>; 655*4882a593Smuzhiyun #size-cells = <0>; 656*4882a593Smuzhiyun reg = <0>; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun endpoint@0 { 659*4882a593Smuzhiyun reg = <0>; 660*4882a593Smuzhiyun remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun endpoint@1 { 664*4882a593Smuzhiyun reg = <1>; 665*4882a593Smuzhiyun remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 666*4882a593Smuzhiyun }; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun tcon_tv0_out: port@1 { 670*4882a593Smuzhiyun #address-cells = <1>; 671*4882a593Smuzhiyun #size-cells = <0>; 672*4882a593Smuzhiyun reg = <1>; 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun endpoint@1 { 675*4882a593Smuzhiyun reg = <1>; 676*4882a593Smuzhiyun remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 677*4882a593Smuzhiyun }; 678*4882a593Smuzhiyun }; 679*4882a593Smuzhiyun }; 680*4882a593Smuzhiyun }; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun #undef CLK_BUS_TCON_TV0 683*4882a593Smuzhiyun #undef RST_BUS_TCON_TV0 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun... 686