1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 HDMI Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun The HDMI Encoder supports the HDMI video and audio outputs, and does 11*4882a593Smuzhiyun CEC. It is one end of the pipeline. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunmaintainers: 14*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 15*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun oneOf: 20*4882a593Smuzhiyun - const: allwinner,sun4i-a10-hdmi 21*4882a593Smuzhiyun - const: allwinner,sun5i-a10s-hdmi 22*4882a593Smuzhiyun - const: allwinner,sun6i-a31-hdmi 23*4882a593Smuzhiyun - items: 24*4882a593Smuzhiyun - const: allwinner,sun7i-a20-hdmi 25*4882a593Smuzhiyun - const: allwinner,sun5i-a10s-hdmi 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun oneOf: 35*4882a593Smuzhiyun - items: 36*4882a593Smuzhiyun - description: The HDMI interface clock 37*4882a593Smuzhiyun - description: The HDMI module clock 38*4882a593Smuzhiyun - description: The first video PLL 39*4882a593Smuzhiyun - description: The second video PLL 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun - items: 42*4882a593Smuzhiyun - description: The HDMI interface clock 43*4882a593Smuzhiyun - description: The HDMI module clock 44*4882a593Smuzhiyun - description: The HDMI DDC clock 45*4882a593Smuzhiyun - description: The first video PLL 46*4882a593Smuzhiyun - description: The second video PLL 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun clock-names: 49*4882a593Smuzhiyun oneOf: 50*4882a593Smuzhiyun - items: 51*4882a593Smuzhiyun - const: ahb 52*4882a593Smuzhiyun - const: mod 53*4882a593Smuzhiyun - const: pll-0 54*4882a593Smuzhiyun - const: pll-1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun - items: 57*4882a593Smuzhiyun - const: ahb 58*4882a593Smuzhiyun - const: mod 59*4882a593Smuzhiyun - const: ddc 60*4882a593Smuzhiyun - const: pll-0 61*4882a593Smuzhiyun - const: pll-1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun resets: 64*4882a593Smuzhiyun maxItems: 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun dmas: 67*4882a593Smuzhiyun items: 68*4882a593Smuzhiyun - description: DDC Transmission DMA Channel 69*4882a593Smuzhiyun - description: DDC Reception DMA Channel 70*4882a593Smuzhiyun - description: Audio Transmission DMA Channel 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dma-names: 73*4882a593Smuzhiyun items: 74*4882a593Smuzhiyun - const: ddc-tx 75*4882a593Smuzhiyun - const: ddc-rx 76*4882a593Smuzhiyun - const: audio-tx 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun ports: 79*4882a593Smuzhiyun type: object 80*4882a593Smuzhiyun description: | 81*4882a593Smuzhiyun A ports node with endpoint definitions as defined in 82*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun properties: 85*4882a593Smuzhiyun "#address-cells": 86*4882a593Smuzhiyun const: 1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun "#size-cells": 89*4882a593Smuzhiyun const: 0 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun port@0: 92*4882a593Smuzhiyun type: object 93*4882a593Smuzhiyun description: | 94*4882a593Smuzhiyun Input endpoints of the controller. 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun port@1: 97*4882a593Smuzhiyun type: object 98*4882a593Smuzhiyun description: | 99*4882a593Smuzhiyun Output endpoints of the controller. Usually an HDMI 100*4882a593Smuzhiyun connector. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun required: 103*4882a593Smuzhiyun - "#address-cells" 104*4882a593Smuzhiyun - "#size-cells" 105*4882a593Smuzhiyun - port@0 106*4882a593Smuzhiyun - port@1 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun additionalProperties: false 109*4882a593Smuzhiyun 110*4882a593Smuzhiyunrequired: 111*4882a593Smuzhiyun - compatible 112*4882a593Smuzhiyun - reg 113*4882a593Smuzhiyun - interrupts 114*4882a593Smuzhiyun - clocks 115*4882a593Smuzhiyun - clock-names 116*4882a593Smuzhiyun - dmas 117*4882a593Smuzhiyun - dma-names 118*4882a593Smuzhiyun 119*4882a593Smuzhiyunif: 120*4882a593Smuzhiyun properties: 121*4882a593Smuzhiyun compatible: 122*4882a593Smuzhiyun contains: 123*4882a593Smuzhiyun const: allwinner,sun6i-a31-hdmi 124*4882a593Smuzhiyun 125*4882a593Smuzhiyunthen: 126*4882a593Smuzhiyun properties: 127*4882a593Smuzhiyun clocks: 128*4882a593Smuzhiyun minItems: 5 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun clock-names: 131*4882a593Smuzhiyun minItems: 5 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun required: 134*4882a593Smuzhiyun - resets 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunadditionalProperties: false 137*4882a593Smuzhiyun 138*4882a593Smuzhiyunexamples: 139*4882a593Smuzhiyun - | 140*4882a593Smuzhiyun #include <dt-bindings/clock/sun4i-a10-ccu.h> 141*4882a593Smuzhiyun #include <dt-bindings/dma/sun4i-a10.h> 142*4882a593Smuzhiyun #include <dt-bindings/reset/sun4i-a10-ccu.h> 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun hdmi: hdmi@1c16000 { 145*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-hdmi"; 146*4882a593Smuzhiyun reg = <0x01c16000 0x1000>; 147*4882a593Smuzhiyun interrupts = <58>; 148*4882a593Smuzhiyun clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, 149*4882a593Smuzhiyun <&ccu CLK_PLL_VIDEO0_2X>, 150*4882a593Smuzhiyun <&ccu CLK_PLL_VIDEO1_2X>; 151*4882a593Smuzhiyun clock-names = "ahb", "mod", "pll-0", "pll-1"; 152*4882a593Smuzhiyun dmas = <&dma SUN4I_DMA_NORMAL 16>, 153*4882a593Smuzhiyun <&dma SUN4I_DMA_NORMAL 16>, 154*4882a593Smuzhiyun <&dma SUN4I_DMA_DEDICATED 24>; 155*4882a593Smuzhiyun dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun ports { 158*4882a593Smuzhiyun #address-cells = <1>; 159*4882a593Smuzhiyun #size-cells = <0>; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun hdmi_in: port@0 { 162*4882a593Smuzhiyun #address-cells = <1>; 163*4882a593Smuzhiyun #size-cells = <0>; 164*4882a593Smuzhiyun reg = <0>; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun hdmi_in_tcon0: endpoint@0 { 167*4882a593Smuzhiyun reg = <0>; 168*4882a593Smuzhiyun remote-endpoint = <&tcon0_out_hdmi>; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun hdmi_in_tcon1: endpoint@1 { 172*4882a593Smuzhiyun reg = <1>; 173*4882a593Smuzhiyun remote-endpoint = <&tcon1_out_hdmi>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun hdmi_out: port@1 { 178*4882a593Smuzhiyun reg = <1>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun... 184