1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Display Engine Frontend Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The display engine frontend does formats conversion, scaling,
15*4882a593Smuzhiyun  deinterlacing and color space conversion.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    enum:
20*4882a593Smuzhiyun      - allwinner,sun4i-a10-display-frontend
21*4882a593Smuzhiyun      - allwinner,sun5i-a13-display-frontend
22*4882a593Smuzhiyun      - allwinner,sun6i-a31-display-frontend
23*4882a593Smuzhiyun      - allwinner,sun7i-a20-display-frontend
24*4882a593Smuzhiyun      - allwinner,sun8i-a23-display-frontend
25*4882a593Smuzhiyun      - allwinner,sun8i-a33-display-frontend
26*4882a593Smuzhiyun      - allwinner,sun9i-a80-display-frontend
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  reg:
29*4882a593Smuzhiyun    maxItems: 1
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  interrupts:
32*4882a593Smuzhiyun    maxItems: 1
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  clocks:
35*4882a593Smuzhiyun    items:
36*4882a593Smuzhiyun      - description: The frontend interface clock
37*4882a593Smuzhiyun      - description: The frontend module clock
38*4882a593Smuzhiyun      - description: The frontend DRAM clock
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  clock-names:
41*4882a593Smuzhiyun    items:
42*4882a593Smuzhiyun      - const: ahb
43*4882a593Smuzhiyun      - const: mod
44*4882a593Smuzhiyun      - const: ram
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  # FIXME: This should be made required eventually once every SoC will
47*4882a593Smuzhiyun  # have the MBUS declared.
48*4882a593Smuzhiyun  interconnects:
49*4882a593Smuzhiyun    maxItems: 1
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  # FIXME: This should be made required eventually once every SoC will
52*4882a593Smuzhiyun  # have the MBUS declared.
53*4882a593Smuzhiyun  interconnect-names:
54*4882a593Smuzhiyun    const: dma-mem
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  resets:
57*4882a593Smuzhiyun    maxItems: 1
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun  ports:
60*4882a593Smuzhiyun    type: object
61*4882a593Smuzhiyun    description: |
62*4882a593Smuzhiyun      A ports node with endpoint definitions as defined in
63*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt.
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun    properties:
66*4882a593Smuzhiyun      "#address-cells":
67*4882a593Smuzhiyun        const: 1
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun      "#size-cells":
70*4882a593Smuzhiyun        const: 0
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun      port@0:
73*4882a593Smuzhiyun        type: object
74*4882a593Smuzhiyun        description: |
75*4882a593Smuzhiyun          Input endpoints of the controller.
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun      port@1:
78*4882a593Smuzhiyun        type: object
79*4882a593Smuzhiyun        description: |
80*4882a593Smuzhiyun          Output endpoints of the controller.
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun    required:
83*4882a593Smuzhiyun      - "#address-cells"
84*4882a593Smuzhiyun      - "#size-cells"
85*4882a593Smuzhiyun      - port@1
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun    additionalProperties: false
88*4882a593Smuzhiyun
89*4882a593Smuzhiyunrequired:
90*4882a593Smuzhiyun  - compatible
91*4882a593Smuzhiyun  - reg
92*4882a593Smuzhiyun  - interrupts
93*4882a593Smuzhiyun  - clocks
94*4882a593Smuzhiyun  - clock-names
95*4882a593Smuzhiyun  - resets
96*4882a593Smuzhiyun  - ports
97*4882a593Smuzhiyun
98*4882a593SmuzhiyunadditionalProperties: false
99*4882a593Smuzhiyun
100*4882a593Smuzhiyunexamples:
101*4882a593Smuzhiyun  - |
102*4882a593Smuzhiyun    #include <dt-bindings/clock/sun4i-a10-ccu.h>
103*4882a593Smuzhiyun    #include <dt-bindings/reset/sun4i-a10-ccu.h>
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun    fe0: display-frontend@1e00000 {
106*4882a593Smuzhiyun        compatible = "allwinner,sun4i-a10-display-frontend";
107*4882a593Smuzhiyun        reg = <0x01e00000 0x20000>;
108*4882a593Smuzhiyun        interrupts = <47>;
109*4882a593Smuzhiyun        clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
110*4882a593Smuzhiyun                 <&ccu CLK_DRAM_DE_FE0>;
111*4882a593Smuzhiyun        clock-names = "ahb", "mod",
112*4882a593Smuzhiyun                      "ram";
113*4882a593Smuzhiyun        resets = <&ccu RST_DE_FE0>;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun        ports {
116*4882a593Smuzhiyun            #address-cells = <1>;
117*4882a593Smuzhiyun            #size-cells = <0>;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun            fe0_out: port@1 {
120*4882a593Smuzhiyun                #address-cells = <1>;
121*4882a593Smuzhiyun                #size-cells = <0>;
122*4882a593Smuzhiyun                reg = <1>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun                fe0_out_be0: endpoint@0 {
125*4882a593Smuzhiyun                    reg = <0>;
126*4882a593Smuzhiyun                    remote-endpoint = <&be0_in_fe0>;
127*4882a593Smuzhiyun                };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun                fe0_out_be1: endpoint@1 {
130*4882a593Smuzhiyun                    reg = <1>;
131*4882a593Smuzhiyun                    remote-endpoint = <&be1_in_fe0>;
132*4882a593Smuzhiyun                };
133*4882a593Smuzhiyun            };
134*4882a593Smuzhiyun        };
135*4882a593Smuzhiyun    };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun...
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