1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Display Engine Backend Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The display engine backend exposes layers and sprites to the system.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    enum:
19*4882a593Smuzhiyun      - allwinner,sun4i-a10-display-backend
20*4882a593Smuzhiyun      - allwinner,sun5i-a13-display-backend
21*4882a593Smuzhiyun      - allwinner,sun6i-a31-display-backend
22*4882a593Smuzhiyun      - allwinner,sun7i-a20-display-backend
23*4882a593Smuzhiyun      - allwinner,sun8i-a23-display-backend
24*4882a593Smuzhiyun      - allwinner,sun8i-a33-display-backend
25*4882a593Smuzhiyun      - allwinner,sun9i-a80-display-backend
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  reg:
28*4882a593Smuzhiyun    minItems: 1
29*4882a593Smuzhiyun    maxItems: 2
30*4882a593Smuzhiyun    items:
31*4882a593Smuzhiyun      - description: Display Backend registers
32*4882a593Smuzhiyun      - description: SAT registers
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  reg-names:
35*4882a593Smuzhiyun    minItems: 1
36*4882a593Smuzhiyun    maxItems: 2
37*4882a593Smuzhiyun    items:
38*4882a593Smuzhiyun      - const: be
39*4882a593Smuzhiyun      - const: sat
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  interrupts:
42*4882a593Smuzhiyun    maxItems: 1
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  clocks:
45*4882a593Smuzhiyun    minItems: 3
46*4882a593Smuzhiyun    maxItems: 4
47*4882a593Smuzhiyun    items:
48*4882a593Smuzhiyun      - description: The backend interface clock
49*4882a593Smuzhiyun      - description: The backend module clock
50*4882a593Smuzhiyun      - description: The backend DRAM clock
51*4882a593Smuzhiyun      - description: The SAT clock
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  clock-names:
54*4882a593Smuzhiyun    minItems: 3
55*4882a593Smuzhiyun    maxItems: 4
56*4882a593Smuzhiyun    items:
57*4882a593Smuzhiyun      - const: ahb
58*4882a593Smuzhiyun      - const: mod
59*4882a593Smuzhiyun      - const: ram
60*4882a593Smuzhiyun      - const: sat
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun  resets:
63*4882a593Smuzhiyun    minItems: 1
64*4882a593Smuzhiyun    maxItems: 2
65*4882a593Smuzhiyun    items:
66*4882a593Smuzhiyun      - description: The Backend reset line
67*4882a593Smuzhiyun      - description: The SAT reset line
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun  reset-names:
70*4882a593Smuzhiyun    minItems: 1
71*4882a593Smuzhiyun    maxItems: 2
72*4882a593Smuzhiyun    items:
73*4882a593Smuzhiyun      - const: be
74*4882a593Smuzhiyun      - const: sat
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun  # FIXME: This should be made required eventually once every SoC will
77*4882a593Smuzhiyun  # have the MBUS declared.
78*4882a593Smuzhiyun  interconnects:
79*4882a593Smuzhiyun    maxItems: 1
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun  # FIXME: This should be made required eventually once every SoC will
82*4882a593Smuzhiyun  # have the MBUS declared.
83*4882a593Smuzhiyun  interconnect-names:
84*4882a593Smuzhiyun    const: dma-mem
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun  ports:
87*4882a593Smuzhiyun    type: object
88*4882a593Smuzhiyun    description: |
89*4882a593Smuzhiyun      A ports node with endpoint definitions as defined in
90*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt.
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun    properties:
93*4882a593Smuzhiyun      "#address-cells":
94*4882a593Smuzhiyun        const: 1
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun      "#size-cells":
97*4882a593Smuzhiyun        const: 0
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun      port@0:
100*4882a593Smuzhiyun        type: object
101*4882a593Smuzhiyun        description: |
102*4882a593Smuzhiyun          Input endpoints of the controller.
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun      port@1:
105*4882a593Smuzhiyun        type: object
106*4882a593Smuzhiyun        description: |
107*4882a593Smuzhiyun          Output endpoints of the controller.
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun    required:
110*4882a593Smuzhiyun      - "#address-cells"
111*4882a593Smuzhiyun      - "#size-cells"
112*4882a593Smuzhiyun      - port@0
113*4882a593Smuzhiyun      - port@1
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun    additionalProperties: false
116*4882a593Smuzhiyun
117*4882a593Smuzhiyunrequired:
118*4882a593Smuzhiyun  - compatible
119*4882a593Smuzhiyun  - reg
120*4882a593Smuzhiyun  - interrupts
121*4882a593Smuzhiyun  - clocks
122*4882a593Smuzhiyun  - clock-names
123*4882a593Smuzhiyun  - resets
124*4882a593Smuzhiyun  - ports
125*4882a593Smuzhiyun
126*4882a593SmuzhiyunadditionalProperties: false
127*4882a593Smuzhiyun
128*4882a593Smuzhiyunif:
129*4882a593Smuzhiyun  properties:
130*4882a593Smuzhiyun    compatible:
131*4882a593Smuzhiyun      contains:
132*4882a593Smuzhiyun        const: allwinner,sun8i-a33-display-backend
133*4882a593Smuzhiyun
134*4882a593Smuzhiyunthen:
135*4882a593Smuzhiyun  properties:
136*4882a593Smuzhiyun    reg:
137*4882a593Smuzhiyun      minItems: 2
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun    reg-names:
140*4882a593Smuzhiyun      minItems: 2
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun    clocks:
143*4882a593Smuzhiyun      minItems: 4
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun    clock-names:
146*4882a593Smuzhiyun      minItems: 4
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun    resets:
149*4882a593Smuzhiyun      minItems: 2
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun    reset-names:
152*4882a593Smuzhiyun      minItems: 2
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun  required:
155*4882a593Smuzhiyun    - reg-names
156*4882a593Smuzhiyun    - reset-names
157*4882a593Smuzhiyun
158*4882a593Smuzhiyunelse:
159*4882a593Smuzhiyun  properties:
160*4882a593Smuzhiyun    reg:
161*4882a593Smuzhiyun      maxItems: 1
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun    reg-names:
164*4882a593Smuzhiyun      maxItems: 1
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun    clocks:
167*4882a593Smuzhiyun      maxItems: 3
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun    clock-names:
170*4882a593Smuzhiyun      maxItems: 3
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun    resets:
173*4882a593Smuzhiyun      maxItems: 1
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun    reset-names:
176*4882a593Smuzhiyun      maxItems: 1
177*4882a593Smuzhiyun
178*4882a593Smuzhiyunexamples:
179*4882a593Smuzhiyun  - |
180*4882a593Smuzhiyun    /*
181*4882a593Smuzhiyun     * This comes from the clock/sun4i-a10-ccu.h and
182*4882a593Smuzhiyun     * reset/sun4i-a10-ccu.h headers, but we can't include them since
183*4882a593Smuzhiyun     * it would trigger a bunch of warnings for redefinitions of
184*4882a593Smuzhiyun     * symbols with the other example.
185*4882a593Smuzhiyun     */
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun    #define CLK_AHB_DE_BE0	42
188*4882a593Smuzhiyun    #define CLK_DRAM_DE_BE0	140
189*4882a593Smuzhiyun    #define CLK_DE_BE0		144
190*4882a593Smuzhiyun    #define RST_DE_BE0		5
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun    display-backend@1e60000 {
193*4882a593Smuzhiyun        compatible = "allwinner,sun4i-a10-display-backend";
194*4882a593Smuzhiyun        reg = <0x01e60000 0x10000>;
195*4882a593Smuzhiyun        interrupts = <47>;
196*4882a593Smuzhiyun        clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
197*4882a593Smuzhiyun                 <&ccu CLK_DRAM_DE_BE0>;
198*4882a593Smuzhiyun        clock-names = "ahb", "mod",
199*4882a593Smuzhiyun                      "ram";
200*4882a593Smuzhiyun        resets = <&ccu RST_DE_BE0>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun        ports {
203*4882a593Smuzhiyun            #address-cells = <1>;
204*4882a593Smuzhiyun            #size-cells = <0>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun            port@0 {
207*4882a593Smuzhiyun                #address-cells = <1>;
208*4882a593Smuzhiyun                #size-cells = <0>;
209*4882a593Smuzhiyun                reg = <0>;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun                endpoint@0 {
212*4882a593Smuzhiyun                    reg = <0>;
213*4882a593Smuzhiyun                    remote-endpoint = <&fe0_out_be0>;
214*4882a593Smuzhiyun                };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun                endpoint@1 {
217*4882a593Smuzhiyun                    reg = <1>;
218*4882a593Smuzhiyun                    remote-endpoint = <&fe1_out_be0>;
219*4882a593Smuzhiyun                };
220*4882a593Smuzhiyun            };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun            port@1 {
223*4882a593Smuzhiyun                #address-cells = <1>;
224*4882a593Smuzhiyun                #size-cells = <0>;
225*4882a593Smuzhiyun                reg = <1>;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun                endpoint@0 {
228*4882a593Smuzhiyun                    reg = <0>;
229*4882a593Smuzhiyun                    remote-endpoint = <&tcon0_in_be0>;
230*4882a593Smuzhiyun                };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun                endpoint@1 {
233*4882a593Smuzhiyun                    reg = <1>;
234*4882a593Smuzhiyun                    remote-endpoint = <&tcon1_in_be0>;
235*4882a593Smuzhiyun                };
236*4882a593Smuzhiyun            };
237*4882a593Smuzhiyun        };
238*4882a593Smuzhiyun    };
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun  - |
241*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun    /*
244*4882a593Smuzhiyun     * This comes from the clock/sun8i-a23-a33-ccu.h and
245*4882a593Smuzhiyun     * reset/sun8i-a23-a33-ccu.h headers, but we can't include them
246*4882a593Smuzhiyun     * since it would trigger a bunch of warnings for redefinitions of
247*4882a593Smuzhiyun     * symbols with the other example.
248*4882a593Smuzhiyun     */
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun    #define CLK_BUS_DE_BE	40
251*4882a593Smuzhiyun    #define CLK_BUS_SAT		46
252*4882a593Smuzhiyun    #define CLK_DRAM_DE_BE	84
253*4882a593Smuzhiyun    #define CLK_DE_BE		85
254*4882a593Smuzhiyun    #define RST_BUS_DE_BE	21
255*4882a593Smuzhiyun    #define RST_BUS_SAT		27
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun    display-backend@1e60000 {
258*4882a593Smuzhiyun        compatible = "allwinner,sun8i-a33-display-backend";
259*4882a593Smuzhiyun        reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
260*4882a593Smuzhiyun        reg-names = "be", "sat";
261*4882a593Smuzhiyun        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
262*4882a593Smuzhiyun        clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
263*4882a593Smuzhiyun                 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
264*4882a593Smuzhiyun        clock-names = "ahb", "mod",
265*4882a593Smuzhiyun                      "ram", "sat";
266*4882a593Smuzhiyun        resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
267*4882a593Smuzhiyun        reset-names = "be", "sat";
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun        ports {
270*4882a593Smuzhiyun            #address-cells = <1>;
271*4882a593Smuzhiyun            #size-cells = <0>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun            port@0 {
274*4882a593Smuzhiyun                reg = <0>;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun                endpoint {
277*4882a593Smuzhiyun                    remote-endpoint = <&fe0_out_be0>;
278*4882a593Smuzhiyun                };
279*4882a593Smuzhiyun            };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun            port@1 {
282*4882a593Smuzhiyun                reg = <1>;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun                endpoint {
285*4882a593Smuzhiyun                    remote-endpoint = <&drc0_in_be0>;
286*4882a593Smuzhiyun                };
287*4882a593Smuzhiyun            };
288*4882a593Smuzhiyun        };
289*4882a593Smuzhiyun    };
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun...
292