1*4882a593Smuzhiyun* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", 5*4882a593Smuzhiyun "jedec,lpddr2-s4" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- density : <u32> representing density in Mb (Mega bits) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- io-width : <u32> representing bus width. Possible values are 8, 16, and 32 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe following optional properties represent the minimum value of some AC 20*4882a593Smuzhiyuntiming parameters of the DDR device in terms of number of clock cycles. 21*4882a593SmuzhiyunThese values shall be obtained from the device data-sheet. 22*4882a593Smuzhiyun- tRRD-min-tck 23*4882a593Smuzhiyun- tWTR-min-tck 24*4882a593Smuzhiyun- tXP-min-tck 25*4882a593Smuzhiyun- tRTP-min-tck 26*4882a593Smuzhiyun- tCKE-min-tck 27*4882a593Smuzhiyun- tRPab-min-tck 28*4882a593Smuzhiyun- tRCD-min-tck 29*4882a593Smuzhiyun- tWR-min-tck 30*4882a593Smuzhiyun- tRASmin-min-tck 31*4882a593Smuzhiyun- tCKESR-min-tck 32*4882a593Smuzhiyun- tFAW-min-tck 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunChild nodes: 35*4882a593Smuzhiyun- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". 36*4882a593Smuzhiyun "lpddr2-timings" provides AC timing parameters of the device for 37*4882a593Smuzhiyun a given speed-bin. The user may provide the timings for as many 38*4882a593Smuzhiyun speed-bins as is required. Please see Documentation/devicetree/ 39*4882a593Smuzhiyun bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunelpida_ECB240ABACN : lpddr2 { 44*4882a593Smuzhiyun compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; 45*4882a593Smuzhiyun density = <2048>; 46*4882a593Smuzhiyun io-width = <32>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun tRPab-min-tck = <3>; 49*4882a593Smuzhiyun tRCD-min-tck = <3>; 50*4882a593Smuzhiyun tWR-min-tck = <3>; 51*4882a593Smuzhiyun tRASmin-min-tck = <3>; 52*4882a593Smuzhiyun tRRD-min-tck = <2>; 53*4882a593Smuzhiyun tWTR-min-tck = <2>; 54*4882a593Smuzhiyun tXP-min-tck = <2>; 55*4882a593Smuzhiyun tRTP-min-tck = <2>; 56*4882a593Smuzhiyun tCKE-min-tck = <3>; 57*4882a593Smuzhiyun tCKESR-min-tck = <3>; 58*4882a593Smuzhiyun tFAW-min-tck = <8>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { 61*4882a593Smuzhiyun compatible = "jedec,lpddr2-timings"; 62*4882a593Smuzhiyun min-freq = <10000000>; 63*4882a593Smuzhiyun max-freq = <400000000>; 64*4882a593Smuzhiyun tRPab = <21000>; 65*4882a593Smuzhiyun tRCD = <18000>; 66*4882a593Smuzhiyun tWR = <15000>; 67*4882a593Smuzhiyun tRAS-min = <42000>; 68*4882a593Smuzhiyun tRRD = <10000>; 69*4882a593Smuzhiyun tWTR = <7500>; 70*4882a593Smuzhiyun tXP = <7500>; 71*4882a593Smuzhiyun tRTP = <7500>; 72*4882a593Smuzhiyun tCKESR = <15000>; 73*4882a593Smuzhiyun tDQSCK-max = <5500>; 74*4882a593Smuzhiyun tFAW = <50000>; 75*4882a593Smuzhiyun tZQCS = <90000>; 76*4882a593Smuzhiyun tZQCL = <360000>; 77*4882a593Smuzhiyun tZQinit = <1000000>; 78*4882a593Smuzhiyun tRAS-max-ns = <70000>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { 82*4882a593Smuzhiyun compatible = "jedec,lpddr2-timings"; 83*4882a593Smuzhiyun min-freq = <10000000>; 84*4882a593Smuzhiyun max-freq = <200000000>; 85*4882a593Smuzhiyun tRPab = <21000>; 86*4882a593Smuzhiyun tRCD = <18000>; 87*4882a593Smuzhiyun tWR = <15000>; 88*4882a593Smuzhiyun tRAS-min = <42000>; 89*4882a593Smuzhiyun tRRD = <10000>; 90*4882a593Smuzhiyun tWTR = <10000>; 91*4882a593Smuzhiyun tXP = <7500>; 92*4882a593Smuzhiyun tRTP = <7500>; 93*4882a593Smuzhiyun tCKESR = <15000>; 94*4882a593Smuzhiyun tDQSCK-max = <5500>; 95*4882a593Smuzhiyun tFAW = <50000>; 96*4882a593Smuzhiyun tZQCS = <90000>; 97*4882a593Smuzhiyun tZQCL = <360000>; 98*4882a593Smuzhiyun tZQinit = <1000000>; 99*4882a593Smuzhiyun tRAS-max-ns = <70000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun} 103