1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 CRYP bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Lionel Debieve <lionel.debieve@st.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun enum: 15*4882a593Smuzhiyun - st,stm32f756-cryp 16*4882a593Smuzhiyun - st,stm32mp1-cryp 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun maxItems: 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clocks: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupts: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun resets: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - compatible 32*4882a593Smuzhiyun - reg 33*4882a593Smuzhiyun - clocks 34*4882a593Smuzhiyun - interrupts 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunadditionalProperties: false 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunexamples: 39*4882a593Smuzhiyun - | 40*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 41*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 42*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 43*4882a593Smuzhiyun cryp@54001000 { 44*4882a593Smuzhiyun compatible = "st,stm32mp1-cryp"; 45*4882a593Smuzhiyun reg = <0x54001000 0x400>; 46*4882a593Smuzhiyun interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 47*4882a593Smuzhiyun clocks = <&rcc CRYP1>; 48*4882a593Smuzhiyun resets = <&rcc CRYP1_R>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun... 52