1*4882a593SmuzhiyunRockchip Electronics And Security Accelerator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "rockchip,rk3288-crypto" 5*4882a593Smuzhiyun- reg: Base physical address of the engine and length of memory mapped 6*4882a593Smuzhiyun region 7*4882a593Smuzhiyun- interrupts: Interrupt number 8*4882a593Smuzhiyun- clocks: Reference to the clocks about crypto 9*4882a593Smuzhiyun- clock-names: "aclk" used to clock data 10*4882a593Smuzhiyun "hclk" used to clock data 11*4882a593Smuzhiyun "sclk" used to clock crypto accelerator 12*4882a593Smuzhiyun "apb_pclk" used to clock dma 13*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 14*4882a593Smuzhiyun See ../reset/reset.txt for details. 15*4882a593Smuzhiyun- reset-names: Must include the name "crypto-rst". 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExamples: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun crypto: cypto-controller@ff8a0000 { 20*4882a593Smuzhiyun compatible = "rockchip,rk3288-crypto"; 21*4882a593Smuzhiyun reg = <0xff8a0000 0x4000>; 22*4882a593Smuzhiyun interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 23*4882a593Smuzhiyun clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 24*4882a593Smuzhiyun <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 25*4882a593Smuzhiyun clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 26*4882a593Smuzhiyun resets = <&cru SRST_CRYPTO>; 27*4882a593Smuzhiyun reset-names = "crypto-rst"; 28*4882a593Smuzhiyun }; 29