1*4882a593SmuzhiyunQualcomm crypto engine driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : should be "qcom,crypto-v5.1" 6*4882a593Smuzhiyun- reg : specifies base physical address and size of the registers map 7*4882a593Smuzhiyun- clocks : phandle to clock-controller plus clock-specifier pair 8*4882a593Smuzhiyun- clock-names : "iface" clocks register interface 9*4882a593Smuzhiyun "bus" clocks data transfer interface 10*4882a593Smuzhiyun "core" clocks rest of the crypto block 11*4882a593Smuzhiyun- dmas : DMA specifiers for tx and rx dma channels. For more see 12*4882a593Smuzhiyun Documentation/devicetree/bindings/dma/dma.txt 13*4882a593Smuzhiyun- dma-names : DMA request names should be "rx" and "tx" 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun crypto@fd45a000 { 17*4882a593Smuzhiyun compatible = "qcom,crypto-v5.1"; 18*4882a593Smuzhiyun reg = <0xfd45a000 0x6000>; 19*4882a593Smuzhiyun clocks = <&gcc GCC_CE2_AHB_CLK>, 20*4882a593Smuzhiyun <&gcc GCC_CE2_AXI_CLK>, 21*4882a593Smuzhiyun <&gcc GCC_CE2_CLK>; 22*4882a593Smuzhiyun clock-names = "iface", "bus", "core"; 23*4882a593Smuzhiyun dmas = <&cryptobam 2>, <&cryptobam 3>; 24*4882a593Smuzhiyun dma-names = "rx", "tx"; 25*4882a593Smuzhiyun }; 26