1*4882a593SmuzhiyunPicochip picoXcell SPAcc (Security Protocol Accelerator) bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPicochip picoXcell devices contain crypto offload engines that may be used for 4*4882a593SmuzhiyunIPSEC and femtocell layer 2 ciphering. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine 8*4882a593Smuzhiyun "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. 9*4882a593Smuzhiyun - reg : Offset and length of the register set for this device 10*4882a593Smuzhiyun - interrupts : The interrupt line from the SPAcc. 11*4882a593Smuzhiyun - ref-clock : The input clock that drives the SPAcc. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample SPAcc node: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunspacc@10000 { 16*4882a593Smuzhiyun compatible = "picochip,spacc-ipsec"; 17*4882a593Smuzhiyun reg = <0x100000 0x10000>; 18*4882a593Smuzhiyun interrupt-parent = <&vic0>; 19*4882a593Smuzhiyun interrupts = <24>; 20*4882a593Smuzhiyun ref-clock = <&ipsec_clk>, "ref"; 21*4882a593Smuzhiyun}; 22