1*4882a593SmuzhiyunMediaTek cryptographic accelerators 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "mediatek,eip97-crypto" 5*4882a593Smuzhiyun- reg: Address and length of the register set for the device 6*4882a593Smuzhiyun- interrupts: Should contain the five crypto engines interrupts in numeric 7*4882a593Smuzhiyun order. These are global system and four descriptor rings. 8*4882a593Smuzhiyun- clocks: the clock used by the core 9*4882a593Smuzhiyun- clock-names: Must contain "cryp". 10*4882a593Smuzhiyun- power-domains: Must contain a reference to the PM domain. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun crypto: crypto@1b240000 { 15*4882a593Smuzhiyun compatible = "mediatek,eip97-crypto"; 16*4882a593Smuzhiyun reg = <0 0x1b240000 0 0x20000>; 17*4882a593Smuzhiyun interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, 18*4882a593Smuzhiyun <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, 19*4882a593Smuzhiyun <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, 20*4882a593Smuzhiyun <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, 21*4882a593Smuzhiyun <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 22*4882a593Smuzhiyun clocks = <ðsys CLK_ETHSYS_CRYPTO>; 23*4882a593Smuzhiyun clock-names = "cryp"; 24*4882a593Smuzhiyun power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 25*4882a593Smuzhiyun }; 26