1*4882a593SmuzhiyunImagination Technologies hardware hash accelerator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe hash accelerator provides hardware hashing acceleration for 4*4882a593SmuzhiyunSHA1, SHA224, SHA256 and MD5 hashes 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible : "img,hash-accelerator" 9*4882a593Smuzhiyun- reg : Offset and length of the register set for the module, and the DMA port 10*4882a593Smuzhiyun- interrupts : The designated IRQ line for the hashing module. 11*4882a593Smuzhiyun- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt 12*4882a593Smuzhiyun- dma-names : Should be "tx" 13*4882a593Smuzhiyun- clocks : Clock specifiers 14*4882a593Smuzhiyun- clock-names : "sys" Used to clock the hash block registers 15*4882a593Smuzhiyun "hash" Used to clock data through the accelerator 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun hash: hash@18149600 { 20*4882a593Smuzhiyun compatible = "img,hash-accelerator"; 21*4882a593Smuzhiyun reg = <0x18149600 0x100>, <0x18101100 0x4>; 22*4882a593Smuzhiyun interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>; 23*4882a593Smuzhiyun dmas = <&dma 8 0xffffffff 0>; 24*4882a593Smuzhiyun dma-names = "tx"; 25*4882a593Smuzhiyun clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; 26*4882a593Smuzhiyun clock-names = "sys", "hash"; 27*4882a593Smuzhiyun }; 28