1*4882a593Smuzhiyun* Hisilicon hip07 Security Accelerator (SEC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must contain one of 5*4882a593Smuzhiyun - "hisilicon,hip06-sec" 6*4882a593Smuzhiyun - "hisilicon,hip07-sec" 7*4882a593Smuzhiyun- reg: Memory addresses and lengths of the memory regions through which 8*4882a593Smuzhiyun this device is controlled. 9*4882a593Smuzhiyun Region 0 has registers to control the backend processing engines. 10*4882a593Smuzhiyun Region 1 has registers for functionality common to all queues. 11*4882a593Smuzhiyun Regions 2-18 have registers for the 16 individual queues which are isolated 12*4882a593Smuzhiyun both in hardware and within the driver. 13*4882a593Smuzhiyun- interrupts: Interrupt specifiers. 14*4882a593Smuzhiyun Refer to interrupt-controller/interrupts.txt for generic interrupt client node 15*4882a593Smuzhiyun bindings. 16*4882a593Smuzhiyun Interrupt 0 is for the SEC unit error queue. 17*4882a593Smuzhiyun Interrupt 2N + 1 is the completion interrupt for queue N. 18*4882a593Smuzhiyun Interrupt 2N + 2 is the error interrupt for queue N. 19*4882a593Smuzhiyun- dma-coherent: The driver assumes coherent dma is possible. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun- iommus: The SEC units are behind smmu-v3 iommus. 23*4882a593Smuzhiyun Refer to iommu/arm,smmu-v3.txt for more information. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunp1_sec_a: crypto@400d2000000 { 28*4882a593Smuzhiyun compatible = "hisilicon,hip07-sec"; 29*4882a593Smuzhiyun reg = <0x400 0xd0000000 0x0 0x10000 30*4882a593Smuzhiyun 0x400 0xd2000000 0x0 0x10000 31*4882a593Smuzhiyun 0x400 0xd2010000 0x0 0x10000 32*4882a593Smuzhiyun 0x400 0xd2020000 0x0 0x10000 33*4882a593Smuzhiyun 0x400 0xd2030000 0x0 0x10000 34*4882a593Smuzhiyun 0x400 0xd2040000 0x0 0x10000 35*4882a593Smuzhiyun 0x400 0xd2050000 0x0 0x10000 36*4882a593Smuzhiyun 0x400 0xd2060000 0x0 0x10000 37*4882a593Smuzhiyun 0x400 0xd2070000 0x0 0x10000 38*4882a593Smuzhiyun 0x400 0xd2080000 0x0 0x10000 39*4882a593Smuzhiyun 0x400 0xd2090000 0x0 0x10000 40*4882a593Smuzhiyun 0x400 0xd20a0000 0x0 0x10000 41*4882a593Smuzhiyun 0x400 0xd20b0000 0x0 0x10000 42*4882a593Smuzhiyun 0x400 0xd20c0000 0x0 0x10000 43*4882a593Smuzhiyun 0x400 0xd20d0000 0x0 0x10000 44*4882a593Smuzhiyun 0x400 0xd20e0000 0x0 0x10000 45*4882a593Smuzhiyun 0x400 0xd20f0000 0x0 0x10000 46*4882a593Smuzhiyun 0x400 0xd2100000 0x0 0x10000>; 47*4882a593Smuzhiyun interrupt-parent = <&p1_mbigen_sec_a>; 48*4882a593Smuzhiyun iommus = <&p1_smmu_alg_a 0x600>; 49*4882a593Smuzhiyun dma-coherent; 50*4882a593Smuzhiyun interrupts = <576 4>, 51*4882a593Smuzhiyun <577 1>, <578 4>, 52*4882a593Smuzhiyun <579 1>, <580 4>, 53*4882a593Smuzhiyun <581 1>, <582 4>, 54*4882a593Smuzhiyun <583 1>, <584 4>, 55*4882a593Smuzhiyun <585 1>, <586 4>, 56*4882a593Smuzhiyun <587 1>, <588 4>, 57*4882a593Smuzhiyun <589 1>, <590 4>, 58*4882a593Smuzhiyun <591 1>, <592 4>, 59*4882a593Smuzhiyun <593 1>, <594 4>, 60*4882a593Smuzhiyun <595 1>, <596 4>, 61*4882a593Smuzhiyun <597 1>, <598 4>, 62*4882a593Smuzhiyun <599 1>, <600 4>, 63*4882a593Smuzhiyun <601 1>, <602 4>, 64*4882a593Smuzhiyun <603 1>, <604 4>, 65*4882a593Smuzhiyun <605 1>, <606 4>, 66*4882a593Smuzhiyun <607 1>, <608 4>; 67*4882a593Smuzhiyun}; 68