1*4882a593SmuzhiyunFreescale SoC SEC Security Engines versions 1.x-2.x-3.x 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : Should contain entries for this and backward compatible 6*4882a593Smuzhiyun SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) 7*4882a593Smuzhiyun e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) 8*4882a593Smuzhiyun warning: SEC1 and SEC2 are mutually exclusive 9*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 10*4882a593Smuzhiyun- interrupts : the SEC's interrupt number 11*4882a593Smuzhiyun- fsl,num-channels : An integer representing the number of channels 12*4882a593Smuzhiyun available. 13*4882a593Smuzhiyun- fsl,channel-fifo-len : An integer representing the number of 14*4882a593Smuzhiyun descriptor pointers each channel fetch fifo can hold. 15*4882a593Smuzhiyun- fsl,exec-units-mask : The bitmask representing what execution units 16*4882a593Smuzhiyun (EUs) are available. It's a single 32-bit cell. EU information 17*4882a593Smuzhiyun should be encoded following the SEC's Descriptor Header Dword 18*4882a593Smuzhiyun EU_SEL0 field documentation, i.e. as follows: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun bit 0 = reserved - should be 0 21*4882a593Smuzhiyun bit 1 = set if SEC has the ARC4 EU (AFEU) 22*4882a593Smuzhiyun bit 2 = set if SEC has the DES/3DES EU (DEU) 23*4882a593Smuzhiyun bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) 24*4882a593Smuzhiyun bit 4 = set if SEC has the random number generator EU (RNG) 25*4882a593Smuzhiyun bit 5 = set if SEC has the public key EU (PKEU) 26*4882a593Smuzhiyun bit 6 = set if SEC has the AES EU (AESU) 27*4882a593Smuzhiyun bit 7 = set if SEC has the Kasumi EU (KEU) 28*4882a593Smuzhiyun bit 8 = set if SEC has the CRC EU (CRCU) 29*4882a593Smuzhiyun bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunremaining bits are reserved for future SEC EUs. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- fsl,descriptor-types-mask : The bitmask representing what descriptors 34*4882a593Smuzhiyun are available. It's a single 32-bit cell. Descriptor type information 35*4882a593Smuzhiyun should be encoded following the SEC's Descriptor Header Dword DESC_TYPE 36*4882a593Smuzhiyun field documentation, i.e. as follows: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type 39*4882a593Smuzhiyun bit 1 = set if SEC supports the ipsec_esp descriptor type 40*4882a593Smuzhiyun bit 2 = set if SEC supports the common_nonsnoop desc. type 41*4882a593Smuzhiyun bit 3 = set if SEC supports the 802.11i AES ccmp desc. type 42*4882a593Smuzhiyun bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type 43*4882a593Smuzhiyun bit 5 = set if SEC supports the srtp descriptor type 44*4882a593Smuzhiyun bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type 45*4882a593Smuzhiyun bit 7 = set if SEC supports the pkeu_assemble descriptor type 46*4882a593Smuzhiyun bit 8 = set if SEC supports the aesu_key_expand_output desc.type 47*4882a593Smuzhiyun bit 9 = set if SEC supports the pkeu_ptmul descriptor type 48*4882a593Smuzhiyun bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type 49*4882a593Smuzhiyun bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ..and so on and so forth. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunExample: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* MPC8548E */ 56*4882a593Smuzhiyun crypto@30000 { 57*4882a593Smuzhiyun compatible = "fsl,sec2.1", "fsl,sec2.0"; 58*4882a593Smuzhiyun reg = <0x30000 0x10000>; 59*4882a593Smuzhiyun interrupts = <29 2>; 60*4882a593Smuzhiyun interrupt-parent = <&mpic>; 61*4882a593Smuzhiyun fsl,num-channels = <4>; 62*4882a593Smuzhiyun fsl,channel-fifo-len = <24>; 63*4882a593Smuzhiyun fsl,exec-units-mask = <0xfe>; 64*4882a593Smuzhiyun fsl,descriptor-types-mask = <0x12b0ebf>; 65*4882a593Smuzhiyun }; 66