1*4882a593SmuzhiyunBinding for NVIDIA Tegra20 CPUFreq 2*4882a593Smuzhiyun================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- clocks: Must contain an entry for the CPU clock. 6*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 7*4882a593Smuzhiyun- operating-points-v2: See ../bindings/opp/opp.txt for details. 8*4882a593Smuzhiyun- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunFor each opp entry in 'operating-points-v2' table: 11*4882a593Smuzhiyun- opp-supported-hw: Two bitfields indicating: 12*4882a593Smuzhiyun On Tegra20: 13*4882a593Smuzhiyun 1. CPU process ID mask 14*4882a593Smuzhiyun 2. SoC speedo ID mask 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun On Tegra30: 17*4882a593Smuzhiyun 1. CPU process ID mask 18*4882a593Smuzhiyun 2. CPU speedo ID mask 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun A bitwise AND is performed against these values and if any bit 21*4882a593Smuzhiyun matches, the OPP gets enabled. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- opp-microvolt: CPU voltage triplet. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties: 26*4882a593Smuzhiyun- cpu-supply: Phandle to the CPU power supply. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun regulators { 30*4882a593Smuzhiyun cpu_reg: regulator0 { 31*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun cpu0_opp_table: opp_table0 { 36*4882a593Smuzhiyun compatible = "operating-points-v2"; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun opp@456000000 { 39*4882a593Smuzhiyun clock-latency-ns = <125000>; 40*4882a593Smuzhiyun opp-microvolt = <825000 825000 1125000>; 41*4882a593Smuzhiyun opp-supported-hw = <0x03 0x0001>; 42*4882a593Smuzhiyun opp-hz = /bits/ 64 <456000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun ... 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun cpus { 49*4882a593Smuzhiyun cpu@0 { 50*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 51*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_CCLK>; 52*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 53*4882a593Smuzhiyun cpu-supply = <&cpu_reg>; 54*4882a593Smuzhiyun #cooling-cells = <2>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57