1*4882a593SmuzhiyunTegra124 CPU frequency scaling driver bindings 2*4882a593Smuzhiyun---------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunBoth required and optional properties listed below must be defined 5*4882a593Smuzhiyununder node /cpus/cpu@0. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 9*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 10*4882a593Smuzhiyun- clock-names: Must include the following entries: 11*4882a593Smuzhiyun - cpu_g: Clock mux for the fast CPU cluster. 12*4882a593Smuzhiyun - pll_x: Fast PLL clocksource. 13*4882a593Smuzhiyun - pll_p: Auxiliary PLL used during fast PLL rate changes. 14*4882a593Smuzhiyun - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun- clock-latency: Specify the possible maximum transition latency for clock, 18*4882a593Smuzhiyun in unit of nanoseconds. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun-------- 22*4882a593Smuzhiyuncpus { 23*4882a593Smuzhiyun #address-cells = <1>; 24*4882a593Smuzhiyun #size-cells = <0>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpu@0 { 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 32*4882a593Smuzhiyun <&tegra_car TEGRA124_CLK_PLL_X>, 33*4882a593Smuzhiyun <&tegra_car TEGRA124_CLK_PLL_P>, 34*4882a593Smuzhiyun <&dfll>; 35*4882a593Smuzhiyun clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 36*4882a593Smuzhiyun clock-latency = <300000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun <...> 40*4882a593Smuzhiyun}; 41