1*4882a593SmuzhiyunSPEAr cpufreq driver 2*4882a593Smuzhiyun------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSPEAr SoC cpufreq driver for CPU frequency scaling. 5*4882a593SmuzhiyunIt supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems 6*4882a593Smuzhiyunwhich share clock across all CPUs. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the 10*4882a593Smuzhiyun increasing order. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- clock-latency: Specify the possible maximum transition latency for clock, in 14*4882a593Smuzhiyun unit of nanoseconds. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunBoth required and optional properties listed above must be defined under node 17*4882a593Smuzhiyun/cpus/cpu@0. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExamples: 20*4882a593Smuzhiyun-------- 21*4882a593Smuzhiyuncpus { 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun <...> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpu@0 { 26*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun <...> 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpufreq_tbl = < 166000 32*4882a593Smuzhiyun 200000 33*4882a593Smuzhiyun 250000 34*4882a593Smuzhiyun 300000 35*4882a593Smuzhiyun 400000 36*4882a593Smuzhiyun 500000 37*4882a593Smuzhiyun 600000 >; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun <...> 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun}; 43