1*4882a593SmuzhiyunGeneric cpufreq driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunIt is a generic DT based cpufreq driver for frequency management. It supports 4*4882a593Smuzhiyunboth uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share 5*4882a593Smuzhiyunclock and voltage across all CPUs. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunBoth required and optional properties listed below must be defined 8*4882a593Smuzhiyununder node /cpus/cpu@0. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- None 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties: 14*4882a593Smuzhiyun- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for 15*4882a593Smuzhiyun details. OPPs *must* be supplied either via DT, i.e. this property, or 16*4882a593Smuzhiyun populated at runtime. 17*4882a593Smuzhiyun- clock-latency: Specify the possible maximum transition latency for clock, 18*4882a593Smuzhiyun in unit of nanoseconds. 19*4882a593Smuzhiyun- voltage-tolerance: Specify the CPU voltage tolerance in percentage. 20*4882a593Smuzhiyun- #cooling-cells: 21*4882a593Smuzhiyun Please refer to 22*4882a593Smuzhiyun Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExamples: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyuncpus { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpu@0 { 31*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun next-level-cache = <&L2>; 34*4882a593Smuzhiyun operating-points = < 35*4882a593Smuzhiyun /* kHz uV */ 36*4882a593Smuzhiyun 792000 1100000 37*4882a593Smuzhiyun 396000 950000 38*4882a593Smuzhiyun 198000 850000 39*4882a593Smuzhiyun >; 40*4882a593Smuzhiyun clock-latency = <61036>; /* two CLK32 periods */ 41*4882a593Smuzhiyun #cooling-cells = <2>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun cpu@1 { 45*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 46*4882a593Smuzhiyun reg = <1>; 47*4882a593Smuzhiyun next-level-cache = <&L2>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun cpu@2 { 51*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 52*4882a593Smuzhiyun reg = <2>; 53*4882a593Smuzhiyun next-level-cache = <&L2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun cpu@3 { 57*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 58*4882a593Smuzhiyun reg = <3>; 59*4882a593Smuzhiyun next-level-cache = <&L2>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62