1*4882a593SmuzhiyunBroadcom AVS mail box and interrupt register bindings 2*4882a593Smuzhiyun===================================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunA total of three DT nodes are required. One node (brcm,avs-cpu-data-mem) 5*4882a593Smuzhiyunreferences the mailbox register used to communicate with the AVS CPU[1]. The 6*4882a593Smuzhiyunsecond node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on 7*4882a593Smuzhiyunthe AVS CPU. The interrupt tells the AVS CPU that it needs to process a 8*4882a593Smuzhiyuncommand sent to it by a driver. Interrupting the AVS CPU is mandatory for 9*4882a593Smuzhiyuncommands to be processed. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe interface also requires a reference to the AVS host interrupt controller, 12*4882a593Smuzhiyunso a driver can react to interrupts generated by the AVS CPU whenever a command 13*4882a593Smuzhiyunhas been processed. See [2] for more information on the brcm,l2-intc node. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun[1] The AVS CPU is an independent co-processor that runs proprietary 16*4882a593Smuzhiyunfirmware. On some SoCs, this firmware supports DFS and DVFS in addition to 17*4882a593SmuzhiyunAdaptive Voltage Scaling. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunNode brcm,avs-cpu-data-mem 23*4882a593Smuzhiyun-------------------------- 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRequired properties: 26*4882a593Smuzhiyun- compatible: must include: brcm,avs-cpu-data-mem and 27*4882a593Smuzhiyun should include: one of brcm,bcm7271-avs-cpu-data-mem or 28*4882a593Smuzhiyun brcm,bcm7268-avs-cpu-data-mem 29*4882a593Smuzhiyun- reg: Specifies base physical address and size of the registers. 30*4882a593Smuzhiyun- interrupts: The interrupt that the AVS CPU will use to interrupt the host 31*4882a593Smuzhiyun when a command completed. 32*4882a593Smuzhiyun- interrupt-names: The name of the interrupt used to interrupt the host. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunOptional properties: 35*4882a593Smuzhiyun- None 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunNode brcm,avs-cpu-l2-intr 38*4882a593Smuzhiyun------------------------- 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunRequired properties: 41*4882a593Smuzhiyun- compatible: must include: brcm,avs-cpu-l2-intr and 42*4882a593Smuzhiyun should include: one of brcm,bcm7271-avs-cpu-l2-intr or 43*4882a593Smuzhiyun brcm,bcm7268-avs-cpu-l2-intr 44*4882a593Smuzhiyun- reg: Specifies base physical address and size of the registers. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunOptional properties: 47*4882a593Smuzhiyun- None 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunExample 51*4882a593Smuzhiyun======= 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun avs_host_l2_intc: interrupt-controller@f04d1200 { 54*4882a593Smuzhiyun #interrupt-cells = <1>; 55*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 56*4882a593Smuzhiyun interrupt-parent = <&intc>; 57*4882a593Smuzhiyun reg = <0xf04d1200 0x48>; 58*4882a593Smuzhiyun interrupt-controller; 59*4882a593Smuzhiyun interrupts = <0x0 0x19 0x0>; 60*4882a593Smuzhiyun interrupt-names = "avs"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun avs-cpu-data-mem@f04c4000 { 64*4882a593Smuzhiyun compatible = "brcm,bcm7271-avs-cpu-data-mem", 65*4882a593Smuzhiyun "brcm,avs-cpu-data-mem"; 66*4882a593Smuzhiyun reg = <0xf04c4000 0x60>; 67*4882a593Smuzhiyun interrupts = <0x1a>; 68*4882a593Smuzhiyun interrupt-parent = <&avs_host_l2_intc>; 69*4882a593Smuzhiyun interrupt-names = "sw_intr"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun avs-cpu-l2-intr@f04d1100 { 73*4882a593Smuzhiyun compatible = "brcm,bcm7271-avs-cpu-l2-intr", 74*4882a593Smuzhiyun "brcm,avs-cpu-l2-intr"; 75*4882a593Smuzhiyun reg = <0xf04d1100 0x10>; 76*4882a593Smuzhiyun }; 77