1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Xilinx Versal clock controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Michal Simek <michal.simek@xilinx.com> 11*4882a593Smuzhiyun - Jolly Shah <jolly.shah@xilinx.com> 12*4882a593Smuzhiyun - Rajan Vaja <rajan.vaja@xilinx.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: | 15*4882a593Smuzhiyun The clock controller is a hardware block of Xilinx versal clock tree. It 16*4882a593Smuzhiyun reads required input clock frequencies from the devicetree and acts as clock 17*4882a593Smuzhiyun provider for all clock consumers of PS clocks. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunselect: false 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun const: xlnx,versal-clk 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun "#clock-cells": 26*4882a593Smuzhiyun const: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun description: List of clock specifiers which are external input 30*4882a593Smuzhiyun clocks to the given clock controller. 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: reference clock 33*4882a593Smuzhiyun - description: alternate reference clock 34*4882a593Smuzhiyun - description: alternate reference clock for programmable logic 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: ref 39*4882a593Smuzhiyun - const: alt_ref 40*4882a593Smuzhiyun - const: pl_alt_ref 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - "#clock-cells" 45*4882a593Smuzhiyun - clocks 46*4882a593Smuzhiyun - clock-names 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun firmware { 53*4882a593Smuzhiyun zynqmp_firmware: zynqmp-firmware { 54*4882a593Smuzhiyun compatible = "xlnx,zynqmp-firmware"; 55*4882a593Smuzhiyun method = "smc"; 56*4882a593Smuzhiyun versal_clk: clock-controller { 57*4882a593Smuzhiyun #clock-cells = <1>; 58*4882a593Smuzhiyun compatible = "xlnx,versal-clk"; 59*4882a593Smuzhiyun clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; 60*4882a593Smuzhiyun clock-names = "ref", "alt_ref", "pl_alt_ref"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun... 65