1*4882a593Smuzhiyun-------------------------------------------------------------------------- 2*4882a593SmuzhiyunDevice Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using 3*4882a593SmuzhiyunZynq MPSoC firmware interface 4*4882a593Smuzhiyun-------------------------------------------------------------------------- 5*4882a593SmuzhiyunThe clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock 6*4882a593Smuzhiyuntree. It reads required input clock frequencies from the devicetree and acts 7*4882a593Smuzhiyunas clock provider for all clock consumers of PS clocks. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunSee clock_bindings.txt for more information on the generic clock bindings. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun - #clock-cells: Must be 1 13*4882a593Smuzhiyun - compatible: Must contain: "xlnx,zynqmp-clk" 14*4882a593Smuzhiyun - clocks: List of clock specifiers which are external input 15*4882a593Smuzhiyun clocks to the given clock controller. Please refer 16*4882a593Smuzhiyun the next section to find the input clocks for a 17*4882a593Smuzhiyun given controller. 18*4882a593Smuzhiyun - clock-names: List of clock names which are exteral input clocks 19*4882a593Smuzhiyun to the given clock controller. Please refer to the 20*4882a593Smuzhiyun clock bindings for more details. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunInput clocks for zynqmp Ultrascale+ clock controller: 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunThe Zynq UltraScale+ MPSoC has one primary and four alternative reference clock 25*4882a593Smuzhiyuninputs. These required clock inputs are: 26*4882a593Smuzhiyun - pss_ref_clk (PS reference clock) 27*4882a593Smuzhiyun - video_clk (reference clock for video system ) 28*4882a593Smuzhiyun - pss_alt_ref_clk (alternative PS reference clock) 29*4882a593Smuzhiyun - aux_ref_clk 30*4882a593Smuzhiyun - gt_crx_ref_clk (transceiver reference clock) 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunThe following strings are optional parameters to the 'clock-names' property in 33*4882a593Smuzhiyunorder to provide an optional (E)MIO clock source: 34*4882a593Smuzhiyun - swdt0_ext_clk 35*4882a593Smuzhiyun - swdt1_ext_clk 36*4882a593Smuzhiyun - gem0_emio_clk 37*4882a593Smuzhiyun - gem1_emio_clk 38*4882a593Smuzhiyun - gem2_emio_clk 39*4882a593Smuzhiyun - gem3_emio_clk 40*4882a593Smuzhiyun - mio_clk_XX # with XX = 00..77 41*4882a593Smuzhiyun - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunOutput clocks are registered based on clock information received 45*4882a593Smuzhiyunfrom firmware. Output clocks indexes are mentioned in 46*4882a593Smuzhiyuninclude/dt-bindings/clock/xlnx-zynqmp-clk.h. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun------- 49*4882a593SmuzhiyunExample 50*4882a593Smuzhiyun------- 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunfirmware { 53*4882a593Smuzhiyun zynqmp_firmware: zynqmp-firmware { 54*4882a593Smuzhiyun compatible = "xlnx,zynqmp-firmware"; 55*4882a593Smuzhiyun method = "smc"; 56*4882a593Smuzhiyun zynqmp_clk: clock-controller { 57*4882a593Smuzhiyun #clock-cells = <1>; 58*4882a593Smuzhiyun compatible = "xlnx,zynqmp-clk"; 59*4882a593Smuzhiyun clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; 60*4882a593Smuzhiyun clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64