1*4882a593SmuzhiyunDevice Tree Clock bindings for arch-vt8500 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be one of the following: 9*4882a593Smuzhiyun "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock 10*4882a593Smuzhiyun "wm,wm8650-pll-clock" - for a WM8650 PLL clock 11*4882a593Smuzhiyun "wm,wm8750-pll-clock" - for a WM8750 PLL clock 12*4882a593Smuzhiyun "wm,wm8850-pll-clock" - for a WM8850 PLL clock 13*4882a593Smuzhiyun "via,vt8500-device-clock" - for a VT/WM device clock 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired properties for PLL clocks: 16*4882a593Smuzhiyun- reg : shall be the control register offset from PMC base for the pll clock. 17*4882a593Smuzhiyun- clocks : shall be the input parent clock phandle for the clock. This should 18*4882a593Smuzhiyun be the reference clock. 19*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunRequired properties for device clocks: 22*4882a593Smuzhiyun- clocks : shall be the input parent clock phandle for the clock. This should 23*4882a593Smuzhiyun be a pll output. 24*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunDevice Clocks 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunDevice clocks are required to have one or both of the following sets of 30*4882a593Smuzhiyunproperties: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunGated device clocks: 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunRequired properties: 36*4882a593Smuzhiyun- enable-reg : shall be the register offset from PMC base for the enable 37*4882a593Smuzhiyun register. 38*4882a593Smuzhiyun- enable-bit : shall be the bit within enable-reg to enable/disable the clock. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunDivisor device clocks: 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunRequired property: 44*4882a593Smuzhiyun- divisor-reg : shall be the register offset from PMC base for the divisor 45*4882a593Smuzhiyun register. 46*4882a593SmuzhiyunOptional property: 47*4882a593Smuzhiyun- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f 48*4882a593Smuzhiyun if not specified. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunFor example: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunref25: ref25M { 54*4882a593Smuzhiyun #clock-cells = <0>; 55*4882a593Smuzhiyun compatible = "fixed-clock"; 56*4882a593Smuzhiyun clock-frequency = <25000000>; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunplla: plla { 60*4882a593Smuzhiyun #clock-cells = <0>; 61*4882a593Smuzhiyun compatible = "wm,wm8650-pll-clock"; 62*4882a593Smuzhiyun clocks = <&ref25>; 63*4882a593Smuzhiyun reg = <0x200>; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunsdhc: sdhc { 67*4882a593Smuzhiyun #clock-cells = <0>; 68*4882a593Smuzhiyun compatible = "via,vt8500-device-clock"; 69*4882a593Smuzhiyun clocks = <&pllb>; 70*4882a593Smuzhiyun divisor-reg = <0x328>; 71*4882a593Smuzhiyun divisor-mask = <0x3f>; 72*4882a593Smuzhiyun enable-reg = <0x254>; 73*4882a593Smuzhiyun enable-bit = <18>; 74*4882a593Smuzhiyun}; 75