1*4882a593Smuzhiyun* Clock bindings for Freescale Vybrid VF610 SOC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "fsl,vf610-ccm" 5*4882a593Smuzhiyun- reg: Address and length of the register set 6*4882a593Smuzhiyun- #clock-cells: Should be <1> 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunOptional properties: 9*4882a593Smuzhiyun- clocks: list of clock identifiers which are external input clocks to the 10*4882a593Smuzhiyun given clock controller. Please refer the next section to find 11*4882a593Smuzhiyun the input clocks for a given controller. 12*4882a593Smuzhiyun- clock-names: list of names of clocks which are exteral input clocks to the 13*4882a593Smuzhiyun given clock controller. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunInput clocks for top clock controller: 16*4882a593Smuzhiyun - sxosc (external crystal oscillator 32KHz, recommended) 17*4882a593Smuzhiyun - fxosc (external crystal oscillator 24MHz, recommended) 18*4882a593Smuzhiyun - audio_ext 19*4882a593Smuzhiyun - enet_ext 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe clock consumer should specify the desired clock by having the clock 22*4882a593SmuzhiyunID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h 23*4882a593Smuzhiyunfor the full list of VF610 clock IDs. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExamples: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunclks: ccm@4006b000 { 28*4882a593Smuzhiyun compatible = "fsl,vf610-ccm"; 29*4882a593Smuzhiyun reg = <0x4006b000 0x1000>; 30*4882a593Smuzhiyun #clock-cells = <1>; 31*4882a593Smuzhiyun clocks = <&sxosc>, <&fxosc>; 32*4882a593Smuzhiyun clock-names = "sxosc", "fxosc"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunuart1: serial@40028000 { 36*4882a593Smuzhiyun compatible = "fsl,vf610-uart"; 37*4882a593Smuzhiyun reg = <0x40028000 0x1000>; 38*4882a593Smuzhiyun interrupts = <0 62 0x04>; 39*4882a593Smuzhiyun clocks = <&clks VF610_CLK_UART1>; 40*4882a593Smuzhiyun clock-names = "ipg"; 41*4882a593Smuzhiyun}; 42