xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ux500.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunClock bindings for ST-Ericsson Ux500 clocks
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties :
4*4882a593Smuzhiyun- compatible : shall contain only one of the following:
5*4882a593Smuzhiyun  "stericsson,u8500-clks"
6*4882a593Smuzhiyun  "stericsson,u8540-clks"
7*4882a593Smuzhiyun  "stericsson,u9540-clks"
8*4882a593Smuzhiyun- reg : shall contain base register location and length for
9*4882a593Smuzhiyun  CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of
10*4882a593Smuzhiyun  CLKRST4, which does not exist.
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunRequired subnodes:
13*4882a593Smuzhiyun- prcmu-clock: a subnode with one clock cell for PRCMU (power,
14*4882a593Smuzhiyun  reset, control unit) clocks. The cell indicates which PRCMU
15*4882a593Smuzhiyun  clock in the prcmu-clock node the consumer wants to use.
16*4882a593Smuzhiyun- prcc-periph-clock: a subnode with two clock cells for
17*4882a593Smuzhiyun  PRCC (programmable reset- and clock controller) peripheral clocks.
18*4882a593Smuzhiyun  The first cell indicates which PRCC block the consumer
19*4882a593Smuzhiyun  wants to use, possible values are 1, 2, 3, 5, 6. The second
20*4882a593Smuzhiyun  cell indicates which clock inside the PRCC block it wants,
21*4882a593Smuzhiyun  possible values are 0 thru 31.
22*4882a593Smuzhiyun- prcc-kernel-clock: a subnode with two clock cells for
23*4882a593Smuzhiyun  PRCC (programmable reset- and clock controller) kernel clocks
24*4882a593Smuzhiyun  The first cell indicates which PRCC block the consumer
25*4882a593Smuzhiyun  wants to use, possible values are 1, 2, 3, 5, 6. The second
26*4882a593Smuzhiyun  cell indicates which clock inside the PRCC block it wants,
27*4882a593Smuzhiyun  possible values are 0 thru 31.
28*4882a593Smuzhiyun- rtc32k-clock: a subnode with zero clock cells for the 32kHz
29*4882a593Smuzhiyun  RTC clock.
30*4882a593Smuzhiyun- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
31*4882a593Smuzhiyun  with zero clock cells.
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunExample:
34*4882a593Smuzhiyun
35*4882a593Smuzhiyunclocks {
36*4882a593Smuzhiyun	compatible = "stericsson,u8500-clks";
37*4882a593Smuzhiyun	/*
38*4882a593Smuzhiyun	 * Registers for the CLKRST block on peripheral
39*4882a593Smuzhiyun	 * groups 1, 2, 3, 5, 6,
40*4882a593Smuzhiyun	 */
41*4882a593Smuzhiyun	reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
42*4882a593Smuzhiyun	    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
43*4882a593Smuzhiyun	    <0xa03cf000 0x1000>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	prcmu_clk: prcmu-clock {
46*4882a593Smuzhiyun		#clock-cells = <1>;
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	prcc_pclk: prcc-periph-clock {
50*4882a593Smuzhiyun		#clock-cells = <2>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	prcc_kclk: prcc-kernel-clock {
54*4882a593Smuzhiyun		#clock-cells = <2>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	rtc_clk: rtc32k-clock {
58*4882a593Smuzhiyun		#clock-cells = <0>;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	smp_twd_clk: smp-twd-clock {
62*4882a593Smuzhiyun		#clock-cells = <0>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun};
65