1*4882a593SmuzhiyunBinding for TI fixed factor rate clock sources. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBinding status: Unstable - ABI compatibility may be broken in the future 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis binding uses the common clock binding[1], and also uses the autoidle 6*4882a593Smuzhiyunsupport from TI autoidle clock [2]. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 9*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible : shall be "ti,fixed-factor-clock". 13*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 14*4882a593Smuzhiyun- ti,clock-div: fixed divider. 15*4882a593Smuzhiyun- ti,clock-mult: fixed multiplier. 16*4882a593Smuzhiyun- clocks: parent clock. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, 20*4882a593Smuzhiyun see [2] 21*4882a593Smuzhiyun- reg: offset for the autoidle register of this clock, see [2] 22*4882a593Smuzhiyun- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2] 23*4882a593Smuzhiyun- ti,set-rate-parent: clk_set_rate is propagated to parent 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun clock { 27*4882a593Smuzhiyun compatible = "ti,fixed-factor-clock"; 28*4882a593Smuzhiyun clocks = <&parentclk>; 29*4882a593Smuzhiyun #clock-cells = <0>; 30*4882a593Smuzhiyun ti,clock-div = <2>; 31*4882a593Smuzhiyun ti,clock-mult = <1>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { 35*4882a593Smuzhiyun #clock-cells = <0>; 36*4882a593Smuzhiyun compatible = "ti,fixed-factor-clock"; 37*4882a593Smuzhiyun clocks = <&dpll_usb_ck>; 38*4882a593Smuzhiyun ti,clock-div = <1>; 39*4882a593Smuzhiyun ti,autoidle-shift = <8>; 40*4882a593Smuzhiyun reg = <0x01b4>; 41*4882a593Smuzhiyun ti,clock-mult = <1>; 42*4882a593Smuzhiyun ti,invert-autoidle-bit; 43*4882a593Smuzhiyun }; 44