1*4882a593SmuzhiyunBinding for Texas Instruments FAPLL clock. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBinding status: Unstable - ABI compatibility may be broken in the future 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis binding uses the common clock binding[1]. It assumes a 6*4882a593Smuzhiyunregister-mapped FAPLL with usually two selectable input clocks 7*4882a593Smuzhiyun(reference clock and bypass clock), and one or more child 8*4882a593Smuzhiyunsyntesizers. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun- compatible : shall be "ti,dm816-fapll-clock" 14*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 15*4882a593Smuzhiyun- clocks : link phandles of parent clocks (clk-ref and clk-bypass) 16*4882a593Smuzhiyun- reg : address and length of the register set for controlling the FAPLL. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExamples: 19*4882a593Smuzhiyun main_fapll: main_fapll { 20*4882a593Smuzhiyun #clock-cells = <1>; 21*4882a593Smuzhiyun compatible = "ti,dm816-fapll-clock"; 22*4882a593Smuzhiyun reg = <0x400 0x40>; 23*4882a593Smuzhiyun clocks = <&sys_clkin_ck &sys_clkin_ck>; 24*4882a593Smuzhiyun clock-indices = <1>, <2>, <3>, <4>, <5>, 25*4882a593Smuzhiyun <6>, <7>; 26*4882a593Smuzhiyun clock-output-names = "main_pll_clk1", 27*4882a593Smuzhiyun "main_pll_clk2", 28*4882a593Smuzhiyun "main_pll_clk3", 29*4882a593Smuzhiyun "main_pll_clk4", 30*4882a593Smuzhiyun "main_pll_clk5", 31*4882a593Smuzhiyun "main_pll_clk6", 32*4882a593Smuzhiyun "main_pll_clk7"; 33*4882a593Smuzhiyun }; 34