1*4882a593SmuzhiyunBinding for TI DaVinci Power Sleep Controller (PSC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe PSC provides power management, clock gating and reset functionality. It is 4*4882a593Smuzhiyunprimarily used for clocking. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: shall be one of: 8*4882a593Smuzhiyun - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX 9*4882a593Smuzhiyun - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX 10*4882a593Smuzhiyun- reg: physical base address and size of the controller's register area 11*4882a593Smuzhiyun- #clock-cells: from common clock binding; shall be set to 1 12*4882a593Smuzhiyun- #power-domain-cells: from generic power domain binding; shall be set to 1. 13*4882a593Smuzhiyun- clocks: phandles to clocks corresponding to the clock-names property 14*4882a593Smuzhiyun- clock-names: list of parent clock names - depends on compatible value 15*4882a593Smuzhiyun - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2", 16*4882a593Smuzhiyun "pll0_sysclk4", "pll0_sysclk6", "async1" 17*4882a593Smuzhiyun - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3" 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- #reset-cells: from reset binding; shall be set to 1 - only applicable when 21*4882a593Smuzhiyun at least one local domain provides a local reset. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunConsumers: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun Clock, power domain and reset consumers shall use the local power domain 26*4882a593Smuzhiyun module ID (LPSC) as the index corresponding to the clock cell. Refer to 27*4882a593Smuzhiyun the device-specific datasheet to find these numbers. NB: Most local 28*4882a593Smuzhiyun domains only provide a clock/power domain and not a reset. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExamples: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun psc0: clock-controller@10000 { 33*4882a593Smuzhiyun compatible = "ti,da850-psc0"; 34*4882a593Smuzhiyun reg = <0x10000 0x1000>; 35*4882a593Smuzhiyun #clock-cells = <1>; 36*4882a593Smuzhiyun #power-domain-cells = <1>; 37*4882a593Smuzhiyun #reset-cells = <1>; 38*4882a593Smuzhiyun clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, 39*4882a593Smuzhiyun <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>; 40*4882a593Smuzhiyun clock_names = "pll0_sysclk1", "pll0_sysclk2", 41*4882a593Smuzhiyun "pll0_sysclk4", "pll0_sysclk6", "async1"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun psc1: clock-controller@227000 { 44*4882a593Smuzhiyun compatible = "ti,da850-psc1"; 45*4882a593Smuzhiyun reg = <0x227000 0x1000>; 46*4882a593Smuzhiyun #clock-cells = <1>; 47*4882a593Smuzhiyun #power-domain-cells = <1>; 48*4882a593Smuzhiyun clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>; 49*4882a593Smuzhiyun clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* consumer */ 53*4882a593Smuzhiyun dsp: dsp@11800000 { 54*4882a593Smuzhiyun compatible = "ti,da850-dsp"; 55*4882a593Smuzhiyun reg = <0x11800000 0x40000>, 56*4882a593Smuzhiyun <0x11e00000 0x8000>, 57*4882a593Smuzhiyun <0x11f00000 0x8000>, 58*4882a593Smuzhiyun <0x01c14044 0x4>, 59*4882a593Smuzhiyun <0x01c14174 0x8>; 60*4882a593Smuzhiyun reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; 61*4882a593Smuzhiyun interrupt-parent = <&intc>; 62*4882a593Smuzhiyun interrupts = <28>; 63*4882a593Smuzhiyun clocks = <&psc0 15>; 64*4882a593Smuzhiyun power-domains = <&psc0 15>; 65*4882a593Smuzhiyun resets = <&psc0 15>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunAlso see: 69*4882a593Smuzhiyun- Documentation/devicetree/bindings/clock/clock-bindings.txt 70*4882a593Smuzhiyun- Documentation/devicetree/bindings/power/power-domain.yaml 71*4882a593Smuzhiyun- Documentation/devicetree/bindings/reset/reset.txt 72