1*4882a593SmuzhiyunBinding for Texas Instruments ADPLL clock. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBinding status: Unstable - ABI compatibility may be broken in the future 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis binding uses the common clock binding[1]. It assumes a 6*4882a593Smuzhiyunregister-mapped ADPLL with two to three selectable input clocks 7*4882a593Smuzhiyunand three to four children. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible : shall be one of "ti,dm814-adpll-s-clock" or 13*4882a593Smuzhiyun "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL 14*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 1. 15*4882a593Smuzhiyun- clocks : link phandles of parent clocks clkinp and clkinpulow, note 16*4882a593Smuzhiyun that the adpll-s-clock also has an optional clkinphif 17*4882a593Smuzhiyun- reg : address and length of the register set for controlling the ADPLL. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExamples: 20*4882a593Smuzhiyun adpll_mpu_ck: adpll@40 { 21*4882a593Smuzhiyun #clock-cells = <1>; 22*4882a593Smuzhiyun compatible = "ti,dm814-adpll-s-clock"; 23*4882a593Smuzhiyun reg = <0x40 0x40>; 24*4882a593Smuzhiyun clocks = <&devosc_ck &devosc_ck &devosc_ck>; 25*4882a593Smuzhiyun clock-names = "clkinp", "clkinpulow", "clkinphif"; 26*4882a593Smuzhiyun clock-output-names = "481c5040.adpll.dcoclkldo", 27*4882a593Smuzhiyun "481c5040.adpll.clkout", 28*4882a593Smuzhiyun "481c5040.adpll.clkoutx2", 29*4882a593Smuzhiyun "481c5040.adpll.clkouthif"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun adpll_dsp_ck: adpll@80 { 33*4882a593Smuzhiyun #clock-cells = <1>; 34*4882a593Smuzhiyun compatible = "ti,dm814-adpll-lj-clock"; 35*4882a593Smuzhiyun reg = <0x80 0x30>; 36*4882a593Smuzhiyun clocks = <&devosc_ck &devosc_ck>; 37*4882a593Smuzhiyun clock-names = "clkinp", "clkinpulow"; 38*4882a593Smuzhiyun clock-output-names = "481c5080.adpll.dcoclkldo", 39*4882a593Smuzhiyun "481c5080.adpll.clkout", 40*4882a593Smuzhiyun "481c5080.adpll.clkoutldo"; 41*4882a593Smuzhiyun }; 42