1*4882a593SmuzhiyunBindings for Texas Instruments CDCE706 programmable 3-PLL clock 2*4882a593Smuzhiyunsynthesizer/multiplier/divider. 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunReference: https://www.ti.com/lit/ds/symlink/cdce706.pdf 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunI2C device node required properties: 7*4882a593Smuzhiyun- compatible: shall be "ti,cdce706". 8*4882a593Smuzhiyun- reg: i2c device address, shall be in range [0x68...0x6b]. 9*4882a593Smuzhiyun- #clock-cells: from common clock binding; shall be set to 1. 10*4882a593Smuzhiyun- clocks: from common clock binding; list of parent clock 11*4882a593Smuzhiyun handles, shall be reference clock(s) connected to CLK_IN0 12*4882a593Smuzhiyun and CLK_IN1 pins. 13*4882a593Smuzhiyun- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0 14*4882a593Smuzhiyun in case of crystal oscillator or differential signal input 15*4882a593Smuzhiyun configuration. Use clk_in0 and clk_in1 in case of independent 16*4882a593Smuzhiyun single-ended LVCMOS inputs configuration. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun clocks { 21*4882a593Smuzhiyun clk54: clk54 { 22*4882a593Smuzhiyun #clock-cells = <0>; 23*4882a593Smuzhiyun compatible = "fixed-clock"; 24*4882a593Smuzhiyun clock-frequency = <54000000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun ... 28*4882a593Smuzhiyun i2c0: i2c-master@d090000 { 29*4882a593Smuzhiyun ... 30*4882a593Smuzhiyun cdce706: clock-synth@69 { 31*4882a593Smuzhiyun compatible = "ti,cdce706"; 32*4882a593Smuzhiyun #clock-cells = <1>; 33*4882a593Smuzhiyun reg = <0x69>; 34*4882a593Smuzhiyun clocks = <&clk54>; 35*4882a593Smuzhiyun clock-names = "clk_in0"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun ... 39*4882a593Smuzhiyun simple-audio-card,codec { 40*4882a593Smuzhiyun ... 41*4882a593Smuzhiyun clocks = <&cdce706 4>; 42*4882a593Smuzhiyun }; 43