1*4882a593Smuzhiyun* Sigma Designs Tango4 Clock Generator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used 4*4882a593Smuzhiyunfor RAM and various peripheral devices). The clock binding described here 5*4882a593Smuzhiyunis applicable to all Tango4 SoCs. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: should be "sigma,tango4-clkgen". 10*4882a593Smuzhiyun- reg: physical base address of the device and length of memory mapped region. 11*4882a593Smuzhiyun- clocks: phandle of the input clock (crystal oscillator). 12*4882a593Smuzhiyun- clock-output-names: should be "cpuclk" and "sysclk". 13*4882a593Smuzhiyun- #clock-cells: should be set to 1. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun clkgen: clkgen@10000 { 18*4882a593Smuzhiyun compatible = "sigma,tango4-clkgen"; 19*4882a593Smuzhiyun reg = <0x10000 0x40>; 20*4882a593Smuzhiyun clocks = <&xtal>; 21*4882a593Smuzhiyun clock-output-names = "cpuclk", "sysclk"; 22*4882a593Smuzhiyun #clock-cells = <1>; 23*4882a593Smuzhiyun }; 24