1*4882a593SmuzhiyunBinding for a ST pll clock driver. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593SmuzhiyunBase address is located to the parent node. See clock binding[2] 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 7*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- compatible : shall be: 12*4882a593Smuzhiyun "st,clkgen-pll0" 13*4882a593Smuzhiyun "st,clkgen-pll1" 14*4882a593Smuzhiyun "st,stih407-clkgen-plla9" 15*4882a593Smuzhiyun "st,stih418-clkgen-plla9" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- #clock-cells : From common clock binding; shall be set to 1. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- clocks : From common clock binding 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- clock-output-names : From common clock binding. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clockgen-a9@92b0000 { 26*4882a593Smuzhiyun compatible = "st,clkgen-c32"; 27*4882a593Smuzhiyun reg = <0x92b0000 0xffff>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clockgen_a9_pll: clockgen-a9-pll { 30*4882a593Smuzhiyun #clock-cells = <1>; 31*4882a593Smuzhiyun compatible = "st,stih407-clkgen-plla9"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks = <&clk_sysin>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock-output-names = "clockgen-a9-pll-odf"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38