1*4882a593SmuzhiyunBinding for a ST multiplexed clock driver. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding supports only simple indexed multiplexers, it does not 4*4882a593Smuzhiyunsupport table based parent index to hardware value translations. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- compatible : shall be: 13*4882a593Smuzhiyun "st,stih407-clkgen-a9-mux" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 0. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- reg : A Base address and length of the register set. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- clocks : from common clock binding 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clk_m_a9: clk-m-a9@92b0000 { 24*4882a593Smuzhiyun #clock-cells = <0>; 25*4882a593Smuzhiyun compatible = "st,stih407-clkgen-a9-mux"; 26*4882a593Smuzhiyun reg = <0x92b0000 0x10000>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks = <&clockgen_a9_pll 0>, 29*4882a593Smuzhiyun <&clockgen_a9_pll 0>, 30*4882a593Smuzhiyun <&clk_s_c0_flexgen 13>, 31*4882a593Smuzhiyun <&clk_m_a9_ext2f_div2>; 32*4882a593Smuzhiyun }; 33