1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Reset Clock Controller Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Gabriel Fernandez <gabriel.fernandez@st.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The RCC IP is both a reset and a clock controller. 14*4882a593Smuzhiyun RCC makes also power management (resume/supend and wakeup interrupt). 15*4882a593Smuzhiyun Please also refer to reset.txt for common reset controller binding usage. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun This binding uses common clock bindings 18*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun Specifying clocks 21*4882a593Smuzhiyun ================= 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun All available clocks are defined as preprocessor macros in 24*4882a593Smuzhiyun dt-bindings/clock/stm32mp1-clks.h header and can be used in device 25*4882a593Smuzhiyun tree sources. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun Specifying softreset control of devices 28*4882a593Smuzhiyun ======================================= 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun Device nodes should specify the reset channel required in their "resets" 31*4882a593Smuzhiyun property, containing a phandle to the reset device node and an index specifying 32*4882a593Smuzhiyun which channel to use. 33*4882a593Smuzhiyun The index is the bit number within the RCC registers bank, starting from RCC 34*4882a593Smuzhiyun base address. 35*4882a593Smuzhiyun It is calculated as: index = register_offset / 4 * 32 + bit_offset. 36*4882a593Smuzhiyun Where bit_offset is the bit offset within the register. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun For example on STM32MP1, for LTDC reset: 39*4882a593Smuzhiyun ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset 40*4882a593Smuzhiyun = 0x180 / 4 * 32 + 0 = 3072 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun The list of valid indices for STM32MP1 is available in: 43*4882a593Smuzhiyun include/dt-bindings/reset-controller/stm32mp1-resets.h 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun This file implements defines like: 46*4882a593Smuzhiyun #define LTDC_R 3072 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunproperties: 49*4882a593Smuzhiyun "#clock-cells": 50*4882a593Smuzhiyun const: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun "#reset-cells": 53*4882a593Smuzhiyun const: 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun compatible: 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun - const: st,stm32mp1-rcc 58*4882a593Smuzhiyun - const: syscon 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun reg: 61*4882a593Smuzhiyun maxItems: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunrequired: 64*4882a593Smuzhiyun - "#clock-cells" 65*4882a593Smuzhiyun - "#reset-cells" 66*4882a593Smuzhiyun - compatible 67*4882a593Smuzhiyun - reg 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunadditionalProperties: false 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunexamples: 72*4882a593Smuzhiyun - | 73*4882a593Smuzhiyun rcc: rcc@50000000 { 74*4882a593Smuzhiyun compatible = "st,stm32mp1-rcc", "syscon"; 75*4882a593Smuzhiyun reg = <0x50000000 0x1000>; 76*4882a593Smuzhiyun #clock-cells = <1>; 77*4882a593Smuzhiyun #reset-cells = <1>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun... 80