1*4882a593SmuzhiyunSTMicroelectronics STM32H7 Reset and Clock Controller 2*4882a593Smuzhiyun===================================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe RCC IP is both a reset and a clock controller. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunPlease refer to clock-bindings.txt for common clock controller binding usage. 7*4882a593SmuzhiyunPlease also refer to reset.txt for common reset controller binding usage. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible: Should be: 11*4882a593Smuzhiyun "st,stm32h743-rcc" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- reg: should be register base and length as documented in the 14*4882a593Smuzhiyun datasheet 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- #reset-cells: 1, see below 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- clocks: External oscillator clock phandle 21*4882a593Smuzhiyun - high speed external clock signal (HSE) 22*4882a593Smuzhiyun - low speed external clock signal (LSE) 23*4882a593Smuzhiyun - external I2S clock (I2S_CKIN) 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties: 26*4882a593Smuzhiyun- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain 27*4882a593Smuzhiyun write protection (RTC clock). 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun rcc: reset-clock-controller@58024400 { 32*4882a593Smuzhiyun compatible = "st,stm32h743-rcc", "st,stm32-rcc"; 33*4882a593Smuzhiyun reg = <0x58024400 0x400>; 34*4882a593Smuzhiyun #reset-cells = <1>; 35*4882a593Smuzhiyun #clock-cells = <1>; 36*4882a593Smuzhiyun clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun st,syscfg = <&pwrcfg>; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunThe peripheral clock consumer should specify the desired clock by 42*4882a593Smuzhiyunhaving the clock ID in its "clocks" phandle cell. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunExample: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun timer5: timer@40000c00 { 47*4882a593Smuzhiyun compatible = "st,stm32-timer"; 48*4882a593Smuzhiyun reg = <0x40000c00 0x400>; 49*4882a593Smuzhiyun interrupts = <50>; 50*4882a593Smuzhiyun clocks = <&rcc TIM5_CK>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunSpecifying softreset control of devices 54*4882a593Smuzhiyun======================================= 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunDevice nodes should specify the reset channel required in their "resets" 57*4882a593Smuzhiyunproperty, containing a phandle to the reset device node and an index specifying 58*4882a593Smuzhiyunwhich channel to use. 59*4882a593SmuzhiyunThe index is the bit number within the RCC registers bank, starting from RCC 60*4882a593Smuzhiyunbase address. 61*4882a593SmuzhiyunIt is calculated as: index = register_offset / 4 * 32 + bit_offset. 62*4882a593SmuzhiyunWhere bit_offset is the bit offset within the register. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunFor example, for CRC reset: 65*4882a593Smuzhiyun crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunExample: 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun timer2 { 70*4882a593Smuzhiyun resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; 71*4882a593Smuzhiyun }; 72