1*4882a593SmuzhiyunSpreadtrum SC9860 Clock Binding 2*4882a593Smuzhiyun------------------------ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: should contain the following compatible strings: 6*4882a593Smuzhiyun - "sprd,sc9860-pmu-gate" 7*4882a593Smuzhiyun - "sprd,sc9860-pll" 8*4882a593Smuzhiyun - "sprd,sc9860-ap-clk" 9*4882a593Smuzhiyun - "sprd,sc9860-aon-prediv" 10*4882a593Smuzhiyun - "sprd,sc9860-apahb-gate" 11*4882a593Smuzhiyun - "sprd,sc9860-aon-gate" 12*4882a593Smuzhiyun - "sprd,sc9860-aonsecure-clk" 13*4882a593Smuzhiyun - "sprd,sc9860-agcp-gate" 14*4882a593Smuzhiyun - "sprd,sc9860-gpu-clk" 15*4882a593Smuzhiyun - "sprd,sc9860-vsp-clk" 16*4882a593Smuzhiyun - "sprd,sc9860-vsp-gate" 17*4882a593Smuzhiyun - "sprd,sc9860-cam-clk" 18*4882a593Smuzhiyun - "sprd,sc9860-cam-gate" 19*4882a593Smuzhiyun - "sprd,sc9860-disp-clk" 20*4882a593Smuzhiyun - "sprd,sc9860-disp-gate" 21*4882a593Smuzhiyun - "sprd,sc9860-apapb-gate" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- #clock-cells: must be 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- clocks : Should be the input parent clock(s) phandle for the clock, this 26*4882a593Smuzhiyun property here just simply shows which clock group the clocks' 27*4882a593Smuzhiyun parents are in, since each clk node would represent many clocks 28*4882a593Smuzhiyun which are defined in the driver. The detailed dependency 29*4882a593Smuzhiyun relationship (i.e. how many parents and which are the parents) 30*4882a593Smuzhiyun are implemented in driver code. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunOptional properties: 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun- reg: Contain the registers base address and length. It must be configured 35*4882a593Smuzhiyun only if no 'sprd,syscon' under the node. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- sprd,syscon: phandle to the syscon which is in the same address area with 38*4882a593Smuzhiyun the clock, and so we can get regmap for the clocks from the 39*4882a593Smuzhiyun syscon device. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pmu_gate: pmu-gate { 44*4882a593Smuzhiyun compatible = "sprd,sc9860-pmu-gate"; 45*4882a593Smuzhiyun sprd,syscon = <&pmu_regs>; 46*4882a593Smuzhiyun clocks = <&ext_26m>; 47*4882a593Smuzhiyun #clock-cells = <1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun pll: pll { 51*4882a593Smuzhiyun compatible = "sprd,sc9860-pll"; 52*4882a593Smuzhiyun sprd,syscon = <&ana_regs>; 53*4882a593Smuzhiyun clocks = <&pmu_gate 0>; 54*4882a593Smuzhiyun #clock-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ap_clk: clock-controller@20000000 { 58*4882a593Smuzhiyun compatible = "sprd,sc9860-ap-clk"; 59*4882a593Smuzhiyun reg = <0 0x20000000 0 0x400>; 60*4882a593Smuzhiyun clocks = <&ext_26m>, <&pll 0>, 61*4882a593Smuzhiyun <&pmu_gate 0>; 62*4882a593Smuzhiyun #clock-cells = <1>; 63*4882a593Smuzhiyun }; 64