1*4882a593SmuzhiyunBinding for the AXS10X Generic PLL clock 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: should be "snps,axs10x-<name>-pll-clock" 9*4882a593Smuzhiyun "snps,axs10x-arc-pll-clock" 10*4882a593Smuzhiyun "snps,axs10x-pgu-pll-clock" 11*4882a593Smuzhiyun- reg: should always contain 2 pairs address - length: first for PLL config 12*4882a593Smuzhiyunregisters and second for corresponding LOCK CGU register. 13*4882a593Smuzhiyun- clocks: shall be the input parent clock phandle for the PLL. 14*4882a593Smuzhiyun- #clock-cells: from common clock binding; Should always be set to 0. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun input-clk: input-clk { 18*4882a593Smuzhiyun clock-frequency = <33333333>; 19*4882a593Smuzhiyun compatible = "fixed-clock"; 20*4882a593Smuzhiyun #clock-cells = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun core-clk: core-clk@80 { 24*4882a593Smuzhiyun compatible = "snps,axs10x-arc-pll-clock"; 25*4882a593Smuzhiyun reg = <0x80 0x10>, <0x100 0x10>; 26*4882a593Smuzhiyun #clock-cells = <0>; 27*4882a593Smuzhiyun clocks = <&input-clk>; 28*4882a593Smuzhiyun }; 29