1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2020 SiFive, Inc. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Sagar Kadam <sagar.kadam@sifive.com> 12*4882a593Smuzhiyun - Paul Walmsley <paul.walmsley@sifive.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: 15*4882a593Smuzhiyun On the FU540 family of SoCs, most system-wide clock and reset integration 16*4882a593Smuzhiyun is via the PRCI IP block. 17*4882a593Smuzhiyun The clock consumer should specify the desired clock via the clock ID 18*4882a593Smuzhiyun macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. 19*4882a593Smuzhiyun These macros begin with PRCI_CLK_. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun The hfclk and rtcclk nodes are required, and represent physical 22*4882a593Smuzhiyun crystals or resonators located on the PCB. These nodes should be present 23*4882a593Smuzhiyun underneath /, rather than /soc. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunproperties: 26*4882a593Smuzhiyun compatible: 27*4882a593Smuzhiyun const: sifive,fu540-c000-prci 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun reg: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clocks: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - description: high frequency clock. 35*4882a593Smuzhiyun - description: RTL clock. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clock-names: 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun - const: hfclk 40*4882a593Smuzhiyun - const: rtcclk 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun "#clock-cells": 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunrequired: 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - clocks 49*4882a593Smuzhiyun - "#clock-cells" 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunadditionalProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun prci: clock-controller@10000000 { 56*4882a593Smuzhiyun compatible = "sifive,fu540-c000-prci"; 57*4882a593Smuzhiyun reg = <0x10000000 0x1000>; 58*4882a593Smuzhiyun clocks = <&hfclk>, <&rtcclk>; 59*4882a593Smuzhiyun #clock-cells = <1>; 60*4882a593Smuzhiyun }; 61