1*4882a593Smuzhiyun* Samsung S3C64xx Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe S3C64xx clock controller generates and supplies clock to various controllers 4*4882a593Smuzhiyunwithin the SoC. The clock binding described here is applicable to all SoCs in 5*4882a593Smuzhiyunthe S3C64xx family. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: should be one of the following. 10*4882a593Smuzhiyun - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. 11*4882a593Smuzhiyun - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 14*4882a593Smuzhiyun region. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- #clock-cells: should be 1. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 19*4882a593Smuzhiyunto specify the clock which they consume. Some of the clocks are available only 20*4882a593Smuzhiyunon a particular S3C64xx SoC and this is specified where applicable. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunAll available clocks are defined as preprocessor macros in 23*4882a593Smuzhiyundt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device 24*4882a593Smuzhiyuntree sources. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExternal clocks: 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 29*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 30*4882a593Smuzhiyunclock-output-names: 31*4882a593Smuzhiyun - "fin_pll" - PLL input clock (xtal/extclk) - required, 32*4882a593Smuzhiyun - "xusbxti" - USB xtal - required, 33*4882a593Smuzhiyun - "iiscdclk0" - I2S0 codec clock - optional, 34*4882a593Smuzhiyun - "iiscdclk1" - I2S1 codec clock - optional, 35*4882a593Smuzhiyun - "iiscdclk2" - I2S2 codec clock - optional, 36*4882a593Smuzhiyun - "pcmcdclk0" - PCM0 codec clock - optional, 37*4882a593Smuzhiyun - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample: Clock controller node: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clock: clock-controller@7e00f000 { 42*4882a593Smuzhiyun compatible = "samsung,s3c6410-clock"; 43*4882a593Smuzhiyun reg = <0x7e00f000 0x1000>; 44*4882a593Smuzhiyun #clock-cells = <1>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunExample: Required external clocks: 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun fin_pll: clock-fin-pll { 50*4882a593Smuzhiyun compatible = "fixed-clock"; 51*4882a593Smuzhiyun clock-output-names = "fin_pll"; 52*4882a593Smuzhiyun clock-frequency = <12000000>; 53*4882a593Smuzhiyun #clock-cells = <0>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun xusbxti: clock-xusbxti { 57*4882a593Smuzhiyun compatible = "fixed-clock"; 58*4882a593Smuzhiyun clock-output-names = "xusbxti"; 59*4882a593Smuzhiyun clock-frequency = <48000000>; 60*4882a593Smuzhiyun #clock-cells = <0>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 64*4882a593Smuzhiyun controller (refer to the standard clock bindings for information about 65*4882a593Smuzhiyun "clocks" and "clock-names" properties): 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun uart0: serial@7f005000 { 68*4882a593Smuzhiyun compatible = "samsung,s3c6400-uart"; 69*4882a593Smuzhiyun reg = <0x7f005000 0x100>; 70*4882a593Smuzhiyun interrupt-parent = <&vic1>; 71*4882a593Smuzhiyun interrupts = <5>; 72*4882a593Smuzhiyun clock-names = "uart", "clk_uart_baud2", 73*4882a593Smuzhiyun "clk_uart_baud3"; 74*4882a593Smuzhiyun clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, 75*4882a593Smuzhiyun <&clock SCLK_UART>; 76*4882a593Smuzhiyun }; 77