1*4882a593Smuzhiyun* Rockchip RK3308 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe RK3308 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the SoC and also implements a reset controller for SoC 5*4882a593Smuzhiyunperipherals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: CRU should be "rockchip,rk3308-cru" 10*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 11*4882a593Smuzhiyun region. 12*4882a593Smuzhiyun- #clock-cells: should be 1. 13*4882a593Smuzhiyun- #reset-cells: should be 1. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional Properties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- rockchip,grf: phandle to the syscon managing the "general register files" 18*4882a593Smuzhiyun If missing, pll rates are not changeable, due to the missing pll lock status. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 21*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 22*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be 23*4882a593Smuzhiyunused in device tree sources. Similar macros exist for the reset sources in 24*4882a593Smuzhiyunthese files. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExternal clocks: 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 29*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 30*4882a593Smuzhiyunclock-output-names: 31*4882a593Smuzhiyun - "xin24m" - crystal input - required, 32*4882a593Smuzhiyun - "xin32k" - rtc clock - optional, 33*4882a593Smuzhiyun - "mclk_i2sx_xch_in" - external I2S or SPDIF clock - optional, 34*4882a593Smuzhiyun - "mac_clkin" - external MAC clock - optional 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: Clock controller node: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun cru: clock-controller@ff500000 { 39*4882a593Smuzhiyun compatible = "rockchip,rk3308-cru"; 40*4882a593Smuzhiyun reg = <0x0 0xff500000 0x0 0x1000>; 41*4882a593Smuzhiyun rockchip,grf = <&grf>; 42*4882a593Smuzhiyun #clock-cells = <1>; 43*4882a593Smuzhiyun #reset-cells = <1>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 47*4882a593Smuzhiyun controller: 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun uart0: serial@ff0a0000 { 50*4882a593Smuzhiyun compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 51*4882a593Smuzhiyun reg = <0x0 0xff0a0000 0x0 0x100>; 52*4882a593Smuzhiyun interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 53*4882a593Smuzhiyun clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 54*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 55*4882a593Smuzhiyun reg-shift = <2>; 56*4882a593Smuzhiyun reg-io-width = <4>; 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun }; 59