1*4882a593Smuzhiyun* Rockchip RK3288 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe RK3288 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the SoC and also implements a reset controller for SoC 5*4882a593Smuzhiyunperipherals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunA revision of this SoC is available: rk3288w. The clock tree is a bit 8*4882a593Smuzhiyundifferent so another dt-compatible is available. Noticed that it is only 9*4882a593Smuzhiyunsetting the difference but there is no automatic revision detection. This 10*4882a593Smuzhiyunshould be performed by bootloaders. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired Properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in 15*4882a593Smuzhiyun case of this revision of Rockchip rk3288. 16*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 17*4882a593Smuzhiyun region. 18*4882a593Smuzhiyun- #clock-cells: should be 1. 19*4882a593Smuzhiyun- #reset-cells: should be 1. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional Properties: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- rockchip,grf: phandle to the syscon managing the "general register files" 24*4882a593Smuzhiyun If missing pll rates are not changeable, due to the missing pll lock status. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 27*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 28*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be 29*4882a593Smuzhiyunused in device tree sources. Similar macros exist for the reset sources in 30*4882a593Smuzhiyunthese files. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExternal clocks: 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 35*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 36*4882a593Smuzhiyunclock-output-names: 37*4882a593Smuzhiyun - "xin24m" - crystal input - required, 38*4882a593Smuzhiyun - "xin32k" - rtc clock - optional, 39*4882a593Smuzhiyun - "ext_i2s" - external I2S clock - optional, 40*4882a593Smuzhiyun - "ext_hsadc" - external HSADC clock - optional, 41*4882a593Smuzhiyun - "ext_edp_24m" - external display port clock - optional, 42*4882a593Smuzhiyun - "ext_vip" - external VIP clock - optional, 43*4882a593Smuzhiyun - "ext_isp" - external ISP clock - optional, 44*4882a593Smuzhiyun - "ext_jtag" - external JTAG clock - optional 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunExample: Clock controller node: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun cru: cru@20000000 { 49*4882a593Smuzhiyun compatible = "rockchip,rk3188-cru"; 50*4882a593Smuzhiyun reg = <0x20000000 0x1000>; 51*4882a593Smuzhiyun rockchip,grf = <&grf>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #clock-cells = <1>; 54*4882a593Smuzhiyun #reset-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 58*4882a593Smuzhiyun controller: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun uart0: serial@10124000 { 61*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 62*4882a593Smuzhiyun reg = <0x10124000 0x400>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun reg-shift = <2>; 65*4882a593Smuzhiyun reg-io-width = <1>; 66*4882a593Smuzhiyun clocks = <&cru SCLK_UART0>; 67*4882a593Smuzhiyun }; 68